高吞吐率任意倍内插滤波器设计
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摘要
提出了一种高吞吐率用于任意倍内插的并行FARROW滤波器。在串行FARROW内插滤波器的基础上,通过数学推导得出了基于多相分解的并行FARROW内插滤波器。该滤波器由并行FIR滤波器、多输入多输出选择器、累加器和乘加器构成,详细讨论了这些模块在FPGA上的实现方法。仿真试验表明:该并行结构滤波器能够在低时钟速率下提供高吞吐率的任意小数或整数倍内插,实现灵活的采样率变换。
A parallel FARROW filter with high throughput for arbitrary interpolation is proposed in this paper. On the basis of serial FARROW interpolation filter,the parallel FARROW interpolation filter based on polyphase decomposition is obtained by mathematical deduction. This parallel filter is consisted of parallel FIR filters,multi-input multi-output selectors,accumulators and multiplyadders. The implementation of these modules in FPGA is discussed in detail. Simulation results show that this parallel FARROW filter can provide arbitrary decimal or integral multiple interpolations with high throughput at low clock rate. Flexible sampling rate conversion is achieved easily on this parallel architecture filter.
A parallel FARROW filter with high throughput for arbitrary interpolation is proposed in this paper. On the basis of serial FARROW interpolation filter,the parallel FARROW interpolation filter based on polyphase decomposition is obtained by mathematical deduction. This parallel filter is consisted of parallel FIR filters,multi-input multi-output selectors,accumulators and multiplyadders. The implementation of these modules in FPGA is discussed in detail. Simulation results show that this parallel FARROW filter can provide arbitrary decimal or integral multiple interpolations with high throughput at low clock rate. Flexible sampling rate conversion is achieved easily on this parallel architecture filter.
引文
[1]FARROW C W.A continuously variable digital delay element[C]//IEEE International Symposium on Circuits and Systems.Espoo,Finland:IEEE Press,1988:2641-2645.
[2]GARDNER F M.Interpolation in digital modems,I.fundamentals[J].IEEE Transactions on Communications,1993,41(3):501-507.
[3]朱彬,朱晓章,杨仕甫,等.宽带分数延时滤波器的优化设计及FPGA实现[J].现代雷达,2012,34(10):28-31.ZHU Bin,ZHU Xiaozhang,YANG Shifu,et al.Optimization design method and FPGA implementations of wide-bandwidth fractional delay filter[J].Modern Radar,2012,34(10):28-31.
[4]MOU Z J,DUHAMEL P.Fast FIR filtering:algorithms and implementations[J].Signal Processing,1987,13(4):377-384.
[5]TSAO Y C,CHOI K.Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2012,20(2):366-371.
[6]邓军,杨银堂.全数字接收机中一种基于并行流水线与快速FIR算法的插值滤波器结构及其实现[J].电子与信息学报,2010,32(9):2089-2094.DENG Jun,YANG Yintang.Structure of interpolation filter based on parallel pipelining and fast FIR algorithm and its implementation for all digital receiver[J].Journal of Electronics&Information Technology,2010,32(9):2089-2094.
[7]LONG J P,TORRES J A.High throughput Farrow re-samplers utilizing reduced complexity FIR filters[C]//2012IEEE Military Communications Conference.Orlando,FL:IEEE Press,2013:1-6.
[2]GARDNER F M.Interpolation in digital modems,I.fundamentals[J].IEEE Transactions on Communications,1993,41(3):501-507.
[3]朱彬,朱晓章,杨仕甫,等.宽带分数延时滤波器的优化设计及FPGA实现[J].现代雷达,2012,34(10):28-31.ZHU Bin,ZHU Xiaozhang,YANG Shifu,et al.Optimization design method and FPGA implementations of wide-bandwidth fractional delay filter[J].Modern Radar,2012,34(10):28-31.
[4]MOU Z J,DUHAMEL P.Fast FIR filtering:algorithms and implementations[J].Signal Processing,1987,13(4):377-384.
[5]TSAO Y C,CHOI K.Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2012,20(2):366-371.
[6]邓军,杨银堂.全数字接收机中一种基于并行流水线与快速FIR算法的插值滤波器结构及其实现[J].电子与信息学报,2010,32(9):2089-2094.DENG Jun,YANG Yintang.Structure of interpolation filter based on parallel pipelining and fast FIR algorithm and its implementation for all digital receiver[J].Journal of Electronics&Information Technology,2010,32(9):2089-2094.
[7]LONG J P,TORRES J A.High throughput Farrow re-samplers utilizing reduced complexity FIR filters[C]//2012IEEE Military Communications Conference.Orlando,FL:IEEE Press,2013:1-6.