PLLFS快速锁定方法的研究与设计
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摘要
在跳频通信中,锁相环频率合成器(PLLFS)需要在极短的时间内完成频率切换,为此本文分析了典型PLLFS频率锁定时的暂态响应全过程,并提出了一种加速锁定的新环路滤波结构,该结构利用开关二极管的单向导通特性,在频率跳变时加快非线性响应速度,而且不影响频率稳定后的频谱纯度。仿真结果显示,典型滤波结构的锁定时间为219.3μs,而该滤波结构的锁定时间只有52μs,极大的加速了PLLFS的频率切换。
Infrequency-hopping communication, the frequency-switchingprocess of Phase-locked loop frequency synthesizer(PLLFS) needs to be completed in a very short time.Based on this situation,this papercomprehensively analyses the whole transient response of typical PLLFS and designs a newloop filter structureto speed up locking.By using the unidirection continuity of the switching diode, the improved structurespeeds up frequency hopping but does not affect the output spectrum purity.The ADS simulation results show that the locking-time oftypical structure is 219.3 μs, but the improved structure is only 52 and it greatly accelerates PLLFS frequency-switching.
Infrequency-hopping communication, the frequency-switchingprocess of Phase-locked loop frequency synthesizer(PLLFS) needs to be completed in a very short time.Based on this situation,this papercomprehensively analyses the whole transient response of typical PLLFS and designs a newloop filter structureto speed up locking.By using the unidirection continuity of the switching diode, the improved structurespeeds up frequency hopping but does not affect the output spectrum purity.The ADS simulation results show that the locking-time oftypical structure is 219.3 μs, but the improved structure is only 52 and it greatly accelerates PLLFS frequency-switching.
引文
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[15]简科军,马成炎,龚敏,等.采用快速锁定技术的Σ-ΔFractional-N PLL行为仿真[J].电子器件,2007(5):1704-1707.
[2]黄武.一种TD-LTE综测仪中跳频合成器的设计[J].电子设计工程,2014(22):171-173.
[3]Banerjee B.PLL Performance,simulation,and Design.3rd Edirion[C].15th IEEE Internationa Conference on 3rd Edition.Aug.2012,35(21)802-805.
[4]远坂俊昭.锁相环电路设计与应用[M].北京:科学出版社,2006.
[5]徐野.基于锁相环的快速跳频源的设计[D].沈阳:沈阳工业大学,2015.
[6]尹雪曼.宽带锁相式频率合成器快速锁定模式研究[D].上海:复旦大学,2008.
[7]Rhee W,Multi-bit delta-sigma modulation techniqueforfractional-N frequencysynthesizers[D].Ph.D,University of Illinois,Urbana-Champaign,2001.
[8]Rui He,Jun Li.Transient analysis of nonlinear settling behavior in charge-pump phase-locked loop design[C].International Symposium on Circuits and Systems(ISCAS),2009:469-472.
[9]V.Manassewitsch,Frequency Synthesizers,Theory and Design[M].New York:John Wiley&Sons,1987.
[10]Dean Banerjee.PLL Performance,Simulation and Design,4th Edition[M].National Semiconductor Corporation,2006.
[11]陈敏华,李江夏,时翔,等.基于锁定时间分析的锁相环频率合成器[J].微波学报,2012,28(1):57-61.
[12]Shu K,Sanchez-Sinencio E.CMOS PLL Synthesizers:Analysisand Design[M].New York:Springer,2005.
[13]Kuang X F,Wu N J.A fast-settling PLL frequency synthesizer with direct frequency presetting[C]//IEEE International Solid-State Circuits Conference,2006:741-750.
[14]Hanumolu P K,Brownlee M,and Moon Un-Ku.Analysis of charge-pump phase-lock loops[J]//IEEE Trans.on Circuits and Systems I,2004,51(9):1665-1674.
[15]简科军,马成炎,龚敏,等.采用快速锁定技术的Σ-ΔFractional-N PLL行为仿真[J].电子器件,2007(5):1704-1707.