一种位宽可变的CRC校验算法及硬件实现
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摘要
在箭上通信中,数据校验是必不可少的,循环冗余校验CRC就是一种普遍采用的校验方法。本文介绍了箭上设备通信框图,比较目前在箭载计算机中普遍采用的几种基于FPGA的CRC校验算法。在分析不同算法优缺点基础上,提出一种输入数据位宽可变的串行计算算法。该算法耗费资源少,配置灵活,易于移植,适合在各类箭载计算机的FPGA平台上实现CRC校验码实时计算。目前该算法已经过仿真验证,并在新一代运载火箭飞行试验中得到成功应用。
In the communication of the launch vehicle,data verification is essential,and the cyclic redundancy check( CRC) is a commonly used verification method. The communication block diagram of the launch vehicle equipment is introduced,and then the common implementations used on FPGA platform are describled and compared. Based on the analysis of the advantages and disadvantages of these methods,a serial computing algorithm with input data configurable width is proposed. The simulation results show that the algorithm consumes less resources and is easy to be transplanted. It is suitable for implementation on various FPGA platforms applied to the launch vehicle. At present,the algorithm has been successfully verified by simulation and is used in the bus communication of the new generation launch vehicle.
In the communication of the launch vehicle,data verification is essential,and the cyclic redundancy check( CRC) is a commonly used verification method. The communication block diagram of the launch vehicle equipment is introduced,and then the common implementations used on FPGA platform are describled and compared. Based on the analysis of the advantages and disadvantages of these methods,a serial computing algorithm with input data configurable width is proposed. The simulation results show that the algorithm consumes less resources and is easy to be transplanted. It is suitable for implementation on various FPGA platforms applied to the launch vehicle. At present,the algorithm has been successfully verified by simulation and is used in the bus communication of the new generation launch vehicle.
引文
[1]Panda A S,Kumar G L.Comparison of Serial Data-input CRC and Parallel Data-input CRC Design for CRC-8 ATMHEC Employing MLFSR[C]//Proceedings of International Conference on Electronics and Communication Systems.Washington D.C.,USA:IEEE Press,2014:1-4.
[2]Li Bin,Huang Zhiping,Shao Jingsu,et al.Implementation of CRC in 10-Gigabit Ethernet Based on FPGA[J].Applied Mechanics&Materials,2014,599-601:1548-1552.
[3]肖艳艳,何晓雄.基于FPGA的CRC算法的串行和并行实现[J].合肥工业大学学报(自然科学版),2016,39(10):1362-1366.(Xiao Yanyan,He Xiaoxiong.Serial and Parallel Implementation of CRC Algorithm Based on FPGA[J].Journal of Hefei University of Technology(Natural Science),2016,39(10):1362-1366.)
[4]薛俊,段发阶,蒋佳佳,等.基于Matlab的并行循环冗余校验Verilog代码自动生成方法[J].计算机应用,2016,36(9):2503-2507.(Xue Jun,Duan Fajie,Jiang Jiajia,et al.Parallel Cyclic Redundancy Check Verilog Program Generating Method Based on Matlab[J].Journal of Computer Applications,2016,36(9):2503-2507.)
[5]李永基,魏文军.基于LFSR的CRC校验码在FPGA上的实现[J].兰州交通大学学报,2015,34(6):91-94.(Li Yongji,Wei Wenjun.Implementing CRC Checksum by FPGA Based on LFSR[J].Journal of Lanzhou Jiaotong University,2015,34(6):91-94.)
[2]Li Bin,Huang Zhiping,Shao Jingsu,et al.Implementation of CRC in 10-Gigabit Ethernet Based on FPGA[J].Applied Mechanics&Materials,2014,599-601:1548-1552.
[3]肖艳艳,何晓雄.基于FPGA的CRC算法的串行和并行实现[J].合肥工业大学学报(自然科学版),2016,39(10):1362-1366.(Xiao Yanyan,He Xiaoxiong.Serial and Parallel Implementation of CRC Algorithm Based on FPGA[J].Journal of Hefei University of Technology(Natural Science),2016,39(10):1362-1366.)
[4]薛俊,段发阶,蒋佳佳,等.基于Matlab的并行循环冗余校验Verilog代码自动生成方法[J].计算机应用,2016,36(9):2503-2507.(Xue Jun,Duan Fajie,Jiang Jiajia,et al.Parallel Cyclic Redundancy Check Verilog Program Generating Method Based on Matlab[J].Journal of Computer Applications,2016,36(9):2503-2507.)
[5]李永基,魏文军.基于LFSR的CRC校验码在FPGA上的实现[J].兰州交通大学学报,2015,34(6):91-94.(Li Yongji,Wei Wenjun.Implementing CRC Checksum by FPGA Based on LFSR[J].Journal of Lanzhou Jiaotong University,2015,34(6):91-94.)