一种高性能的全数字锁相环设计方案
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摘要
针对实现参考频率和输出的频率近似相等或者近似成整数倍关系时遇到的锁相环设计方案复杂以及高性能的模拟锁相环不适宜于集成化问题,设计了主要由模数转换器、全数字式鉴相器、数字式低通滤波器和数控振荡器等构成的全数字式锁相环。主要利用模数转换器在动态量采集时具有的边沿效应从其采集的大量数据中选择出精度更高的数据用于后级的全数字式鉴相,实现了一种全数字式锁相环。实验结果表明了该方案的正确性及其具有锁定精度高和环路的本底噪声低等特性。
Aiming at the fact that a complex scheme is needed when the two frequencies in the phase locked loop are close to each other or have an approximate integer multiple relationship and the traditional analog phase locked loop is unsuitable for integration and on chip implementation,an all-digital phase locked loop is proposed,which is mainly composed of analog to digital converters,an all-digital phase detector,a digital low pass filter and a digitally controlled oscillator.The analog to digital converters' quantization errors have been greatly suppressed by using the clock cursor effect and digital edge effect and an all-digital phase locked loop with a high performance is achieved.Experiment indicates the correctness of the design scheme and shows that the proposed loop has characteristics of high precision and low noise.
Aiming at the fact that a complex scheme is needed when the two frequencies in the phase locked loop are close to each other or have an approximate integer multiple relationship and the traditional analog phase locked loop is unsuitable for integration and on chip implementation,an all-digital phase locked loop is proposed,which is mainly composed of analog to digital converters,an all-digital phase detector,a digital low pass filter and a digitally controlled oscillator.The analog to digital converters' quantization errors have been greatly suppressed by using the clock cursor effect and digital edge effect and an all-digital phase locked loop with a high performance is achieved.Experiment indicates the correctness of the design scheme and shows that the proposed loop has characteristics of high precision and low noise.
引文
[1]JANG T,JEONG S,JEON D,et al.A Noise Reconfigurable All-digital Phase-locked Loop Using a Switched Capacitor Based Frequency-locked Loop and a Noise Detector[J].IEEE Journal of Solid-State Circuits,2018,53(1):50-65.
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[4]NAMGOONG W.A Modified Proportional-Integral Loop Filter to Suppress DCO Noise in Digital PLL[J].IEEETransactions on Circuits and Systems II:Express Briefs,2018,65(8):974-978.
[5]屈八一,宋焕生,周渭,等.一种新型不同频直接鉴相的锁相环[J].西安电子科技大学学报,2014,42(2):172-177.QU Bayi,SONG Huansheng,ZHOU Wei,et al.Novel Phase-locked Loop with Direct Phase Detection for Two Frequency Different Signals[J].Journal of Xidian University,2014,41(2):172-177.
[6]RYU S,YEO H,LEE Y,et al.A 9.2GHz Digital Phase-locked Loop with Peaking-free Transfer Function[J].IEEEJournal of Solid-State Circuits,2014,49(8):1773-1784.
[7]GOLESTAN S,GUERRERO J M,VASQUEZ J C.Steady-state Linear Kalman Filter-based PLLs for Power Applications:a Second Look[J].IEEE Transactions on Industrial Electronics,2018,65(12):9785-9800.
[8]LIN J M,YANG C Y.A Fast-locking All-digital Phase-locked Loop with Dynamic Loop Bandwidth Adjustment[J].IEEE Transactions on Circuits and Systems I:Regular Papers,2015,62(10):2411-2422.
[9]偶晓娟,周渭,易韦韦,等.精密频率测量边沿效应的特性分析[J].西安电子科技大学学报,2016,43(3):144-148.OU Xiaojuan,ZHOU Wei,YI Weiwei,et al.Characteristic Analysis of the Border Effect in Precision Frequency Measurement[J].Journal of Xidian University,2016,43(3):144-148.
[10]许龙飞,罗丹,周渭,等.一种全面响应时间的频率稳定度测量[J].西安电子科技大学学报,2018,45(1):72-75.XU Longfei,LUO Dan,ZHOU Wei,et al.Method of a Comprehensive Response Time of Frequency Stability[J].Journal of Xidian University,2018,45(1):72-75.
[11]BAI L N,LIU H D,ZHOU W,et al.ADC Border Effect and Suppression of Quantization Error in the Digital Dynamic Measurement[J].Chinese Physical B,2017,26(9):090601.
[2]VILA VALLS J,CLOSAS P,NAVARRO M,et al.Are PLLs Dead?A Tutorial on Kalman Filter-based Techniques for Digital Carrier Synchronization[J].IEEE Aerospace and Electronic Systems Magazine,2017,32(7):28-45.
[3]JANG S C,KIM S W,CHU S H,et al.An Optimum Loop Gain Tracking All-digital PLL Using Autocorrelation of Bang-Bang Phase-frequency Detection[J].IEEE Transactions on Circuits and Systems II:Express Briefs,2015,62(9):836-840.
[4]NAMGOONG W.A Modified Proportional-Integral Loop Filter to Suppress DCO Noise in Digital PLL[J].IEEETransactions on Circuits and Systems II:Express Briefs,2018,65(8):974-978.
[5]屈八一,宋焕生,周渭,等.一种新型不同频直接鉴相的锁相环[J].西安电子科技大学学报,2014,42(2):172-177.QU Bayi,SONG Huansheng,ZHOU Wei,et al.Novel Phase-locked Loop with Direct Phase Detection for Two Frequency Different Signals[J].Journal of Xidian University,2014,41(2):172-177.
[6]RYU S,YEO H,LEE Y,et al.A 9.2GHz Digital Phase-locked Loop with Peaking-free Transfer Function[J].IEEEJournal of Solid-State Circuits,2014,49(8):1773-1784.
[7]GOLESTAN S,GUERRERO J M,VASQUEZ J C.Steady-state Linear Kalman Filter-based PLLs for Power Applications:a Second Look[J].IEEE Transactions on Industrial Electronics,2018,65(12):9785-9800.
[8]LIN J M,YANG C Y.A Fast-locking All-digital Phase-locked Loop with Dynamic Loop Bandwidth Adjustment[J].IEEE Transactions on Circuits and Systems I:Regular Papers,2015,62(10):2411-2422.
[9]偶晓娟,周渭,易韦韦,等.精密频率测量边沿效应的特性分析[J].西安电子科技大学学报,2016,43(3):144-148.OU Xiaojuan,ZHOU Wei,YI Weiwei,et al.Characteristic Analysis of the Border Effect in Precision Frequency Measurement[J].Journal of Xidian University,2016,43(3):144-148.
[10]许龙飞,罗丹,周渭,等.一种全面响应时间的频率稳定度测量[J].西安电子科技大学学报,2018,45(1):72-75.XU Longfei,LUO Dan,ZHOU Wei,et al.Method of a Comprehensive Response Time of Frequency Stability[J].Journal of Xidian University,2018,45(1):72-75.
[11]BAI L N,LIU H D,ZHOU W,et al.ADC Border Effect and Suppression of Quantization Error in the Digital Dynamic Measurement[J].Chinese Physical B,2017,26(9):090601.