三维闪存中基于钨互连的空气隙结构的制备工艺
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摘要
将空气隙应用于逻辑器件后段金属互连线中可以有效降低互连线间的寄生电容,提升电路信号传输速度,但制备过程仍具有一定的困难。基于三维闪存(3D NAND)中后段(BEOL)W的自对准双重图形化(SADP)工艺,利用湿法刻蚀的方法在W化学机械平坦化(CMP)之后去除SiO_2介质层,然后再利用化学气相淀积(CVD)法淀积一层台阶覆盖率较低的介质在金属互连线层内形成空气隙。采用空气隙结构代替原来的SiO_2介质层可降低约37.4%的寄生电容,且薄膜的台阶覆盖率会进一步降低电容。TCAD仿真和电性能测试结果表明,采用该方法制备的空气隙结构可降低互连延迟。
The application of air-gap to the back-end metal interconnect of the logic devices can effectively reduce the parasitic capacitance between interconnects and improve signal transmission speeds of circuits. But the manufacture process has many difficulties. Based on the W self-aligned double patterning(SADP) process of the back-end-of-line(BEOL)of 3 D NAND flash, the wet etching method was used to remove the SiO_2 dielectric layer after W chemical mechanical planarization(CMP). Then the chemical vapor deposition(CVD) method was used to deposit a dielectric film with low step coverage to form an air-gap within the metal interconnect layer. Using air-gap instead of the original SiO_2 dielectric layer can achieve a 37.4% reduction in parasitic capacitance, and the step coverage of the film further affects the capacitance reduction. The TCAD simulation and electrical test results show that the interconnect delay can be reduced effectively by the air-gap structure prepared with this rnethod.
The application of air-gap to the back-end metal interconnect of the logic devices can effectively reduce the parasitic capacitance between interconnects and improve signal transmission speeds of circuits. But the manufacture process has many difficulties. Based on the W self-aligned double patterning(SADP) process of the back-end-of-line(BEOL)of 3 D NAND flash, the wet etching method was used to remove the SiO_2 dielectric layer after W chemical mechanical planarization(CMP). Then the chemical vapor deposition(CVD) method was used to deposit a dielectric film with low step coverage to form an air-gap within the metal interconnect layer. Using air-gap instead of the original SiO_2 dielectric layer can achieve a 37.4% reduction in parasitic capacitance, and the step coverage of the film further affects the capacitance reduction. The TCAD simulation and electrical test results show that the interconnect delay can be reduced effectively by the air-gap structure prepared with this rnethod.
引文
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[11] 孙玉红.金属连线间形成空气隙的改进工艺研究[J].集成电路应用,2018,35(7):53-55.SUN Y H. Change airgap process to improve the metal bridge in RF switch devices[J]. Application of IC, 2018,35(7):53-55(in Chinese).
[12] SHIEH B, SARASWAT K C, MCVITTIE J P, et al. Air-gap formation during IMD deposition to lower interconnect capacitance[J]. IEEE Electron Device Letters, 1998, 19(1):16-18.
[2] YAMASHITA K, ODANAKA S. Impact of crosstalk on delay time and a hierarchy of interconnects[C]// Proceedings of International Electron Devices Meeting. San Francisco, CA, USA, 1998:291-294.
[3] KU B W, DEBACKER P, MILOJEVIC D, et al. Physical design solutions to tackle FEOL/BEOL degradation in gate-level monolithic 3D ICs[C]// Proceedings of International Symposium on Low Power Electronics and Design. San Francisco, CA, USA,2016:76-81.
[4] CHANDRASHEKAR A. Method for forming tungsten contacts and interconnects with small critical dimensions:US20100267230 A1 [P]. 2010-10-21.
[5] INGERLY D, AGRAWAL A, ASCAZUBI R, et al. Low-k interconnect stack with metal-insulator-metal capacitors for 22 nm high volume manufacturing[C]// Proceedings of Interconnect Technology Conference. San Jose,CA,USA, 2012:1-3.
[6] HOOFMAN R J O M, VERHEIJDEN G J A M, MICHELON J, et al. Challenges in the implementation of low-k dielectrics in the back-end of line[J]. Microelectronic Engineering, 2005, 80(5):337-344.
[7] GAILLARD F, de PONTCHARRA J, GOSSET L G, et al. Chemical etching solutions for air gap formation using a sacrificial oxide/polymer approach[J]. Microelectronic Engineering, 2006, 83(11/12):2309-2313.
[8] KUMARESAN V, WILSON C J, VERDONCK P, et al. Simulation and measurement of the capacitance benefit of air gap interconnects for advanced technology nodes[J]. Microelectronic Engineering, 2014, 120(6):90-94.
[9] FISCHER K, CHANG H K, INGERLY D, et al. Perfor-mance enhancement for 14 nm high volume manufacturing microprocessor and system on a chip processes[C]// Proceedings of International Interconnect Technology Conference/Advanced Metallization Conference. San Jose, CA, USA, 2016:5-7.
[10] 尹匀丰, 汪辉. 空气隙Cu互连结构热应力史研究[J]. 半导体技术, 2010, 35(4):352-356. YIN J F, WANG H. Study on thermal stress history in air-gap/Cu interconnect [J]. Semiconductor Technology, 2010, 35(4):352-356 (in Chinese).
[11] 孙玉红.金属连线间形成空气隙的改进工艺研究[J].集成电路应用,2018,35(7):53-55.SUN Y H. Change airgap process to improve the metal bridge in RF switch devices[J]. Application of IC, 2018,35(7):53-55(in Chinese).
[12] SHIEH B, SARASWAT K C, MCVITTIE J P, et al. Air-gap formation during IMD deposition to lower interconnect capacitance[J]. IEEE Electron Device Letters, 1998, 19(1):16-18.