基于JESD204B的接收端数据链路层设计与实现
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摘要
行业新标准JESD204B支持高达12.5 Gbit/s串行传输速率,是解决数据转换器与逻辑器件之间高速数据传输问题的主流接口。采用四字节并行处理方案实现了JESD204B协议接收端数据链路层电路,完成协议功能的同时将电路工作时钟频率由1.25 GHz降低到312.5 MHz,使其能在CMOS工艺下使用标准数字电路设计流程实现。将Verilog HDL实现的电路与XILINX JESD204B 6.1v版本的发送端IP核进行对接,验证了该方案的可行性。在Design Compiler平台上,采用65 nm LP CMOS工艺数字标准单元库,对设计方案进行了综合评估。实验结果表明,该方案在工作频率和功能方面均能满足JESD204B协议规范。
As a new industry standard, JESD204 B supports up to 12.5 Gbit/s serial transmission rate and is currently the mainstream interface solution for high speed data transmission between data converters and logic devices. A quad-byte parallel processing scheme was used to implement the data link layer circuit of JESD204 B protocol receivers. The protocol function was implemented, and the circuit's operating clock frequency was reduced from 1.25 GHz to 312.5 MHz, which enabled it to be implemented at the standard digital circuit design flow in a CMOS process. The circuit implemented by Verilog HDL was docked with the sender IP core of XILINX official JESD204 B 6.1 v version to verify the feasibility of this solution. The design was evaluated using the 65 nm LP CMOS process digital standard cell library on the Design Compiler platform. Experimental results showed that this scheme could meet the JESD204 B protocol specifications in all aspects such as working frequency and function.
As a new industry standard, JESD204 B supports up to 12.5 Gbit/s serial transmission rate and is currently the mainstream interface solution for high speed data transmission between data converters and logic devices. A quad-byte parallel processing scheme was used to implement the data link layer circuit of JESD204 B protocol receivers. The protocol function was implemented, and the circuit's operating clock frequency was reduced from 1.25 GHz to 312.5 MHz, which enabled it to be implemented at the standard digital circuit design flow in a CMOS process. The circuit implemented by Verilog HDL was docked with the sender IP core of XILINX official JESD204 B 6.1 v version to verify the feasibility of this solution. The design was evaluated using the 65 nm LP CMOS process digital standard cell library on the Design Compiler platform. Experimental results showed that this scheme could meet the JESD204 B protocol specifications in all aspects such as working frequency and function.
引文
[1] Joint electron device engineering Council.JEDEC standard serial interface for data converters:JESD204B.01 [S/OL].https://www.jedec.org/sites/default/files/ docs/JESD204B-01.pdf,2018-05-16.
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[14] 欧阳靖,姚亚峰,霍兴华,等.JESD204B协议中自同步加解扰电路设计与实现 [J].电子设计工程,2017,25(7):148-151.
[2] SAHEB H,HAIDER S.Scalable high speed serial interface for data converters:using the JESD204B industry standard [C] // IEEE Design & Test Symp.Algiers,Algeria.2015:6-11.
[3] CHATTOPADHYAY B,BHAT S N,NAYAK G,et al.A 12.5 Gbps transmitter for multi-standard SERDES in 40nm low leakage CMOS process [C] // IEEE Int Conf VLSI Des & Embed Syst.Pune,India.2018:13-18.
[4] 田瑞,刘马良.JESD204B协议的高速串行转换器接口 [J].西安电子科技大学学报,2017,44(4):69-74.
[5] YUAN S,WU L,WANG Z,et al.A 70 mW 25 Gb/s quarter-rate SerDes transmitter and receiver chipset with 40 dB of equalization in 65 nm CMOS technology [J].IEEE Trans Circ & Syst I:Regu Pap,2016,63(7):939-949.
[6] 吴让仲,杨敏,刘建,等.基于JESD204B接口协议的接收端电路研制 [J].电子技术,2016,45(11):86-90.
[7] 赵佳.JESD204B接口的研究与实现 [D].西安:西安电子科技大学,2017.
[8] 宋奕霖,王自强.14 Gb/s 高速串行接口发送端电路设计 [J].微电子学,2015,45(1):26-31.
[9] 樊周华.基于JESD204B标准的高速串行接口设计与实现 [D].西安:西安电子科技大学,2016.
[10] WU Z M,ZHANG C,LI F L,et al.High speed serial interface transceiver controller based on JESD204B [C] // IEEE New Circ & Syst Conf.Vancouver,Canada.2016:1-4.
[11] ZHOU Q Q,WANG W,YAO Y F,et al.A qaud_byte implementation of 8B10B decoder in JESD204B protocol [C] // IEEE Intelli Robot Syst.Wuhan,China.2017:137-140.
[12] 李永乾.基于8b/10b编码技术的SerDes接口电路设计 [D].成都:电子科技大学,2010.
[13] 霍兴华,姚亚峰,贾茜茜,等.JESD204B接口协议中的加扰电路设计 [J].电视技术,2014,38(23):64-67.
[14] 欧阳靖,姚亚峰,霍兴华,等.JESD204B协议中自同步加解扰电路设计与实现 [J].电子设计工程,2017,25(7):148-151.