基于高速串行收发器的单芯片光网络单元设计
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摘要
针对工业应用无源光网络开发周期长,灵活性差的缺陷,提出利用现场可编程门阵列内部集成的高速串行收发器代替外接物理层芯片的设计方案。改进分层设计模型和数据帧结构,突发同步字符长度可根据光线路终端收发器突发同步性能在线重配置。板级验证结果表明,系统能够在3.125 Gbit/s速率下完成数据帧接收和突发模式发送,具有兼容性高、复杂度低等诸多优势。
To solve the issues of the long development cycle and poor flexibility of industrial Passive Optical Metwork(PON), we proposed a scheme composed of Field Programmable Gate Array(FPGA) with integrated high-speed serial transceivers instead of external physical layer chip. The hierarchical design model and data frame structure are improved and the character length of burst synchronization can be reconfigured online according to the burst synchronization performance of the optical line terminal transceiver. The results of board level verification show that the system can complete the data frame reception and burst mode transmission at the rate of 3.125 Gbit/s, with advantages of high compatibility and low complexity.
To solve the issues of the long development cycle and poor flexibility of industrial Passive Optical Metwork(PON), we proposed a scheme composed of Field Programmable Gate Array(FPGA) with integrated high-speed serial transceivers instead of external physical layer chip. The hierarchical design model and data frame structure are improved and the character length of burst synchronization can be reconfigured online according to the burst synchronization performance of the optical line terminal transceiver. The results of board level verification show that the system can complete the data frame reception and burst mode transmission at the rate of 3.125 Gbit/s, with advantages of high compatibility and low complexity.
引文
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[4] 郝计军.基于Zynq平台的双PON口EPON ONU SOPC设计[D].济南:山东大学, 2014.
[5] 李永基,魏文军.基于LFSR的CRC校验码在FPGA上的实现[J].兰州交通大学学报,2015.34(6):91-94.
[6] 滑莎,李锋,武磊磊.板间高速数据传输接口的设计与实现[J].无线电工程,2017,47(11):79-82.
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