一种新型路径共享真时延波束合成架构的设计
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  • 英文篇名:Design of a new path-sharing true-time-delay beamformer architecture
  • 作者:党艳杰 ; 梁煜 ; 张为
  • 英文作者:DANG Yanjie;LIANG Yu;ZHANG Wei;School of Microelectronics,Tianjin University;
  • 关键词:多波束 ; 路径共享 ; 真时延 ; 群延时 ; 超宽带
  • 英文关键词:multi-beam;;path-sharing;;true-time-delay;;group delay;;ultra wide band
  • 中文刊名:BJHK
  • 英文刊名:Journal of Beijing University of Aeronautics and Astronautics
  • 机构:天津大学微电子学院;
  • 出版日期:2019-01-24 13:46
  • 出版单位:北京航空航天大学学报
  • 年:2019
  • 期:v.45;No.316
  • 基金:国家重点研发计划(2016YFE0100400)~~
  • 语种:中文;
  • 页:BJHK201906024
  • 页数:7
  • CN:06
  • ISSN:11-2625/V
  • 分类号:211-217
摘要
为满足宽带天线通信系统多输入多输出的要求,提出了一种新型路径共享真时延波束合成架构。通过真时延单元提供的一定延时差弥补信号到达天线的时间差,合成多路信号来提高输出能力。相比于传统的波束合成架构,该架构通过真时延单元共享,节省芯片面积。该架构具有中心对称性与可扩展性,可支持2M个输入和2K个输出。基于HHNEC0. 18μm CMOS工艺设计四入四出波束合成器单元,对提出的架构加以验证。仿真结果表明,工作频带为0. 5~1. 5 GHz,延时分辨率为80 ps、最大延时为720 ps。在天线间距为10. 5 cm的情况下,能够提供±43°和±13°四个扫描角度。输入输出回波损耗≤-10 dB,带内整体增益为约26 dB,增益平坦度≤3 dB。版图面积(包括I/O焊盘和ESD)为3. 69 mm×3. 62 mm。
        In order to meet the requirement of multi-input and multi-output of broadband wireless communication system,a new path-sharing true-time-delay beamformer architecture is proposed in this paper. The output capability is improved by synthesizing multiple signals,compensating the time difference in reaching the antenna with a certain delay difference provided by the true-time-delay unit. Compared with the traditional beamformer architecture,this architecture can save the area of chip by true-time-delay unit sharing. It is not only extensional,supporting 2 M antennas and synthesizing 2 K signal beams,but also symmetrical. Based on HHNEC 0. 18 μm CMOS process,four-in-four-out beamformer is designed to verify the proposed architecture.The simulation results show that this beamformer works over 0. 5-1. 5 GHz and has four antennas,with delay resolution of 80 ps and maximum delay of 720 ps. It can provide four scanning angles of ± 43° and ± 13° for four antennas with 10. 5 cm spacing. The input-output return loss is not more than-10 dB,the gain is about26 dB,and gain flatness is not more than 3 dB. The layout area( including I/O pad and ESD) is 3. 69 mm ×3. 62 mm.
引文
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