65 nm CMOS工艺的低功耗加固12T存储单元设计
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摘要
随着CMOS工艺尺寸的不断缩减,存储单元对高能辐射粒子变得更加敏感,由此产生的软错误和因电荷共享导致的双节点翻转急剧增多.为了提高存储单元的可靠性,提出一种由4个PMOS晶体管和8个NMOS晶体管组成的抗辐射加固12T存储单元,并由NMOS晶体管中的N_1和N_2以及N_3和N_4构成了堆叠结构来降低存储单元的功耗;其基于物理翻转机制避免了存储节点产生负向的瞬态脉冲,在存储节点之间引入的负反馈机制,有效地阻碍了存储单元的翻转.大量的HSPICE仿真结果表明,所提出的存储单元不仅能够完全容忍敏感节点的翻转,还能够部分容忍电荷共享引起的敏感节点对翻转;与已有的存储单元相比,所提出的存储单元的功耗、面积开销、读/写时间平均减小了18.28%, 13.18%, 5.76%和22.68%,并且噪声容限的值较大;结果表明该存储单元在面积开销、存取时间、功耗和稳定性方面取得了很好的折中.
As the size of CMOS processes continues to shrink, memory cells become more sensitive to high-energy radiation particles, and the resulting soft errors and double node upset caused by charge sharing increase dramatically. To improve the reliability of memory cells, a radiation hardened 12 T memory cell consisting of 4 PMOS transistors and 8 NMOS transistors is proposed, moreover, N_1, N_2 and N_3 and N_4 in the NMOS transistor constitute a stack structure to reduce the power consumption of the memory cell; which avoids negative transient pulses generated by storage nodes based on upset physical mechanism, the negative feedback introduced between storage nodes effectively hinders the memory cell upset. Extensive HSPICE simulation results show that the proposed memory cell can not only fully tolerate the upset of sensitive nodes,but also partially tolerate the sensitive node pair upset caused by charge sharing. Compared with other memory cells, the power consumption, area overhead, read time and write time of the proposed memory cell are reduced by 18.28%, 13.18%, 5.76% and 22.68% on average, and the value of the noise margin is larger,the results show that the proposed memory cell make better tradeoff among area overhead, access time,power consumption and stability.
As the size of CMOS processes continues to shrink, memory cells become more sensitive to high-energy radiation particles, and the resulting soft errors and double node upset caused by charge sharing increase dramatically. To improve the reliability of memory cells, a radiation hardened 12 T memory cell consisting of 4 PMOS transistors and 8 NMOS transistors is proposed, moreover, N_1, N_2 and N_3 and N_4 in the NMOS transistor constitute a stack structure to reduce the power consumption of the memory cell; which avoids negative transient pulses generated by storage nodes based on upset physical mechanism, the negative feedback introduced between storage nodes effectively hinders the memory cell upset. Extensive HSPICE simulation results show that the proposed memory cell can not only fully tolerate the upset of sensitive nodes,but also partially tolerate the sensitive node pair upset caused by charge sharing. Compared with other memory cells, the power consumption, area overhead, read time and write time of the proposed memory cell are reduced by 18.28%, 13.18%, 5.76% and 22.68% on average, and the value of the noise margin is larger,the results show that the proposed memory cell make better tradeoff among area overhead, access time,power consumption and stability.
引文
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[8]Jahinuzzaman S M, Rennie D J, Sachdev M. A soft error tolerant10TSRAMbit-cellwithdifferentialreadcapability[J].IEEE Transactions on Nuclear Science, 2009, 56(6):3768-3773
[9]Jung I S, Kim Y B, Lombardi F. A novel sort error hardened10T SRAM cells for low voltage operation[C]//Proceedings of the55thIEEEInternationalMidwestSymposiumonCircuits andsystems.LosAlamitos:IEEEComputerSocietyPress,2012:714-717
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[11]Guo J, Xiao L Y, Mao Z G. Novel low-power and highly reliableradiationhardenedmemorycellfor65 nmCMOStechnology[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2014, 61(7):1994-2001
[12]Qi C H, Xiao L Y, Wang T Q, et al. A highly reliable memory celldesigncombinedwithlayout-levelapproachtotolerant single-event upsets[J]. IEEE Transactions on Device and Materials Reliability, 2016, 16(3):388-395
[13]ReviriegoP,MaestroJA,FlanaganMF.Errordetectionin majoritylogicdecodingofEuclideangeometrylowdensity parity check(EG-LDPC)codes[J]. IEEE Transactions on Very Large Scale Integration Systems, 2013, 21(1):156-159
[14]Guo J, Xiao L Y, Mao Z G, et al. Enhanced memory reliability against multiple cell upsets using decimal matrix code[J]. IEEE TransactionsonVeryLargeScaleIntegrationSystems,2014,22(1):127-135
[15]Naseer R, Draper J. Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs[C]//Proceedings of the34thEuropeanSolid-StateCircuitsConference.LosAlamitos:IEEE Computer Society Press, 2008:222-225
[16]Yang C G, Emre Y, Chakrabarti C. Product code schemes for errorcorrectioninMLCNANDflashmemories[J].IEEE TransactionsonVeryLargeScaleIntegrationSystems,2012,20(12):2302-2314
[17]Naeimi H, DeHon A. Fault secure encoder and decoder for nanomemoryapplications[J].IEEETransactionsonVeryLarge Scale Integration Systems, 2009, 17(4):473-486
[18]Harada R, Mitsuyama Y, Hashimoto M, et al. Neutron induced single event multiple transients with voltage scaling and body biasing[C]//Proceedings of the IEEE International Reliability PhysicsSymposium.LosAlamitos:IEEEComputerSociety Press, 2011:3C.4.1-3C.4.5
[19]Amusan O A, Witulski A F, Massengill L W, et al. Charge collection and charge sharing in a 130 nm CMOS technology[J].IEEE Transactions on Nuclear Science, 2006, 53(6):3253-3258
[20]SheshadriVB,BhuvaBL,ReedRA,etal.Effectsof multi-nodechargecollectioninflip-flopdesignsatadvanced technologynodes[C]//ProceedingsoftheIEEEInternational Reliability Physics Symposium. Los Alamitos:IEEE Computer Society Press, 2010:1026-1030
[21]Zhou Q M, Mohanram K. Gate sizing to radiation harden combinational logic[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(1):155-166
[22]Liang Huaguo, Li Xin, Wang Zhi, et al. Low power latch designforsingleeventupsettolerance[J].JournalofComputer-AidedDesign&ComputerGraphics,2017,29(8):1549-1556(in Chinese)(梁华国,李昕,王志,等.抗单粒子翻转的低功耗锁存器设计[J].计算机辅助设计与图形学学报,2017,29(8):1549-1556)
[23]Katsarou K, Tsiatouhas Y. Soft error interception latch:double node charge sharing SEU tolerant design[J]. Electronics Letters,2015, 51(4):330-332
[24]HuangZhengfeng,FengZhicheng,YaoHuijie,etal.Double node upset tolerant latch based on bybrid TMR[J]. Journal of Computer-AidedDesign&ComputerGraphics,2018,30(5):968-974(in Chinese)(黄正峰,凤志成,姚慧杰,等.基于混合三模冗余的容忍双点翻转锁存器[J].计算机辅助设计与图形学学报,2018,30(5):968-974)
① http://ptm.asu.edu/
[2]Feng Yanjun, Hua Gengxin, Liu Shufen. Radiation hardness for spaceelectronics[J].JournalofAstronautics,2007,28(5):1071-1080(in Chinese)(冯彦君,华更新,刘淑芬.航天电子抗辐射研究综述[J].宇航学报, 2007, 28(5):1071-1080)
[3]Sun Yongjie, Liu Biwei. SEU hardened SRAM design based on DICE cell[J]. Journal of National University of Defense Technology, 2012, 34(4):158-163(in Chinese)(孙永节,刘必慰.基于DICE单元的抗SEU加固SRAM设计[J].国防科技大学学报, 2012, 34(4):158-163)
[4]Mc Lain M L, Barnaby H J, Esqueda I S, et al. Reliability of high performance standard two-edge and radiation hardened by designenclosedgeometrytransistors[C]//Proceedingsofthe IEEEInternationalReliabilityPhysicsSymposium.LosAlamitos:IEEE Computer Society Press, 2009:174-179
[5]Blum D R, Delgado-Frias J G. Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems[J]. IEEE Transactions on Nuclear Science, 2006, 53(3):1564-1573
[6]Liu S F, Reviriego P, Maestro J A. Efficient majority logic fault detection with difference-set codes for memory applications[J].IEEETransactionsonVeryLargeScaleIntegrationSystems,2012, 20(1):148-156
[7]Calin T, Nicolaidis M, Velazco R. Upset hardened memory designforsubmicronCMOStechnology[J].IEEETransactions on Nuclear Science, 1996, 43(6):2874-2878
[8]Jahinuzzaman S M, Rennie D J, Sachdev M. A soft error tolerant10TSRAMbit-cellwithdifferentialreadcapability[J].IEEE Transactions on Nuclear Science, 2009, 56(6):3768-3773
[9]Jung I S, Kim Y B, Lombardi F. A novel sort error hardened10T SRAM cells for low voltage operation[C]//Proceedings of the55thIEEEInternationalMidwestSymposiumonCircuits andsystems.LosAlamitos:IEEEComputerSocietyPress,2012:714-717
[10]Guo J, Xiao L Y, Wang T Q, et al. Soft error hardened memory design for nanoscale complementary metal oxide semiconductortechnology[J].IEEETransactionsonReliability,2015,64(2):596-602
[11]Guo J, Xiao L Y, Mao Z G. Novel low-power and highly reliableradiationhardenedmemorycellfor65 nmCMOStechnology[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2014, 61(7):1994-2001
[12]Qi C H, Xiao L Y, Wang T Q, et al. A highly reliable memory celldesigncombinedwithlayout-levelapproachtotolerant single-event upsets[J]. IEEE Transactions on Device and Materials Reliability, 2016, 16(3):388-395
[13]ReviriegoP,MaestroJA,FlanaganMF.Errordetectionin majoritylogicdecodingofEuclideangeometrylowdensity parity check(EG-LDPC)codes[J]. IEEE Transactions on Very Large Scale Integration Systems, 2013, 21(1):156-159
[14]Guo J, Xiao L Y, Mao Z G, et al. Enhanced memory reliability against multiple cell upsets using decimal matrix code[J]. IEEE TransactionsonVeryLargeScaleIntegrationSystems,2014,22(1):127-135
[15]Naseer R, Draper J. Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs[C]//Proceedings of the34thEuropeanSolid-StateCircuitsConference.LosAlamitos:IEEE Computer Society Press, 2008:222-225
[16]Yang C G, Emre Y, Chakrabarti C. Product code schemes for errorcorrectioninMLCNANDflashmemories[J].IEEE TransactionsonVeryLargeScaleIntegrationSystems,2012,20(12):2302-2314
[17]Naeimi H, DeHon A. Fault secure encoder and decoder for nanomemoryapplications[J].IEEETransactionsonVeryLarge Scale Integration Systems, 2009, 17(4):473-486
[18]Harada R, Mitsuyama Y, Hashimoto M, et al. Neutron induced single event multiple transients with voltage scaling and body biasing[C]//Proceedings of the IEEE International Reliability PhysicsSymposium.LosAlamitos:IEEEComputerSociety Press, 2011:3C.4.1-3C.4.5
[19]Amusan O A, Witulski A F, Massengill L W, et al. Charge collection and charge sharing in a 130 nm CMOS technology[J].IEEE Transactions on Nuclear Science, 2006, 53(6):3253-3258
[20]SheshadriVB,BhuvaBL,ReedRA,etal.Effectsof multi-nodechargecollectioninflip-flopdesignsatadvanced technologynodes[C]//ProceedingsoftheIEEEInternational Reliability Physics Symposium. Los Alamitos:IEEE Computer Society Press, 2010:1026-1030
[21]Zhou Q M, Mohanram K. Gate sizing to radiation harden combinational logic[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(1):155-166
[22]Liang Huaguo, Li Xin, Wang Zhi, et al. Low power latch designforsingleeventupsettolerance[J].JournalofComputer-AidedDesign&ComputerGraphics,2017,29(8):1549-1556(in Chinese)(梁华国,李昕,王志,等.抗单粒子翻转的低功耗锁存器设计[J].计算机辅助设计与图形学学报,2017,29(8):1549-1556)
[23]Katsarou K, Tsiatouhas Y. Soft error interception latch:double node charge sharing SEU tolerant design[J]. Electronics Letters,2015, 51(4):330-332
[24]HuangZhengfeng,FengZhicheng,YaoHuijie,etal.Double node upset tolerant latch based on bybrid TMR[J]. Journal of Computer-AidedDesign&ComputerGraphics,2018,30(5):968-974(in Chinese)(黄正峰,凤志成,姚慧杰,等.基于混合三模冗余的容忍双点翻转锁存器[J].计算机辅助设计与图形学学报,2018,30(5):968-974)
① http://ptm.asu.edu/