基于延迟锁相环和锁频环结构的全数字同步倍频器
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摘要
针对现有基于PLLs/DLLs的全数字化同步倍频器结构存在的不足,提出了一种基于双环结构的全数字同步倍频器。它由延迟锁相环和锁频环共享一个共同的参考时钟信号(F_(REF))构成,不需要任何模拟组件,采用Verilog-HDL语言设计,在Altera DE2-70开发板上实现合成;实验结果表明,所提出的结构相比于现有的结构,能够获得更高频率的输出时钟信号,提供更好的频率分辨率、更好的抖动性能和高倍乘因子。
Aiming at the shortages of existing all-digital synchronous multiplier structure based on PLLs/DLLs,an all-digital synchronous multiplier based on a dual-loop architecture is proposed.It is composed of proposed delaylocked loops and frequency-locked loops that share a common reference clock signal(F_(REF)) and requires no any analog components.The proposed architecture is designed using the Verilog-HDL language and synthesized on the Altera DE2-70 development board.The experimental results show that the proposed architecture,compared with the existing architectures,can generate output clock signal having a higher frequency,provide better frequency resolution and jitter performance as well as high multiplication factor.
Aiming at the shortages of existing all-digital synchronous multiplier structure based on PLLs/DLLs,an all-digital synchronous multiplier based on a dual-loop architecture is proposed.It is composed of proposed delaylocked loops and frequency-locked loops that share a common reference clock signal(F_(REF)) and requires no any analog components.The proposed architecture is designed using the Verilog-HDL language and synthesized on the Altera DE2-70 development board.The experimental results show that the proposed architecture,compared with the existing architectures,can generate output clock signal having a higher frequency,provide better frequency resolution and jitter performance as well as high multiplication factor.
引文
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[2]Mesgarzadeh B,Alvandpour A.A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode[J].IEEE Journal of SolidState Circuits,2009,44(7):1907-1913.
[3]Chung C C,Lee C Y.An All-Digital Phase-Locked Loop for HighSpeed Clock Generation[J].IEEE Journal of Solid-State Circuits,2003,38(2):347-351.
[4]Moorthi S,Meganathan D,Janarthanan D,et al.Low Jitter ADPLL Based Clock Generator for High Speed So C Applications[J].International Journal of Electronics,2009,96(11):1183-1189.
[5]Olsson T,Nilsson P.A Digitally Controlled PLL for So C Applications[J].IEEE Journal of Solid-State Circuits,2004,39(5):751-760.
[6]张陆.基于TDC的全数字锁相环研究与设计[D].南京:南京邮电大学,2014.
[7]Liu X,Feng P,Wu N.Low Power Low Phase Noise Phase Locked Loop Frequency Synthesizer with Fast Locking Mode for 2.4 GHz Applications[J].Japanese Journal of Applied Physics,2014,53(53):853-871.
[8]Casha O,Grech I,Badets F.Analysis of the Spur Characteristics of Edge-Combining DLL Based Frequency Multipliers[J].IEEE Transactions on Circuits and SystemsⅡ,2009,56(2):132-136.
[9]肖帅,孙建波,耿华,等.基于FPGA实现的可变模全数字锁相环[J].电工技术学报,2012,27(4):153-158.
[10]张志文,曾志兵,罗隆福,等.基于新型全数字锁相环的同步倍频技术[J].电力自动化设备,2010,30(2):123-126,130.
[11]Hsieh M T,Sobelman G E.Architectures for Multigigabit WireLinked Clock and Data Recovery[J].IEEE Circuits and Systems Magazine,2008,8(4):45-57.
[12]Bae Y C,Wei G Y.A Mixed PLL/DLL Architecture for Low Jitter Clock Generation[C]//The IEEE International Symposium on Cirquits and Systems,2004.
[13]Sayfullah M.Jitter Analysis of Mixed PLL-DLL Architecture in DRAM Environment[C]//16th International Conference on Mixed Design of Integrated Circuits and Systems,2009.
[14]Peslouan P O L D,Majek C,Taris T,et al.A New Frequency Synthesizers Stabilization Method Based on a Mixed Phase Locked Loop and Delay Locked Loop Architecture[C]//The IEEE International Symposium of Circuits and Systems,2011.
[15]Assaad M,Alser M.An FPGA-Based Design and Implementation of an All-Digital Serializer for Inter Module Communication in So C[J].IEICE Electronics Express,2011,8(23):2017-2023.