一种具有相位噪声跟踪补偿的全数字锁相环频率合成器
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摘要
为了实现频率合成器中的相位噪声跟踪补偿和降低全数字锁相环的复杂性,提出了一种新的基于全数字锁相环的频率合成器。它采用一种低复杂度的数字鉴频鉴相器和非线性相位/频率判决电路以及数控振荡器来显著降低硬件复杂性,同时能够很好地实现噪声跟踪和快速的相位/频率捕获,获得高的频率分辨率(大约6 kHz)和大的线性频率调谐范围。实验结果表明,提出的结构能够实现从100 kHz~6 MHz的可控环路带宽和相当好的带内相位噪声跟踪性能。
A new frequency synthesizer based on all digital phase-locked loop is proposed to realize the phase noise tracking compensation and reduce the complexity of the all digital phase-locked loop.It uses an digital phasefrequency detector and a nonlinear phase/frequency decision circuit as well as a digitally-controlled oscillator with a low complexity to significantly reduces the hardware complexity.At the same time,the proposed architecture can achieve good noise tracking and fast phase/frequency acquisition and high frequency resolution(approximately 6 kHz) and large linear frequency tuning range.The experimental results show that the proposed frequency synthesizer can achieve a programmable loop bandwidth from 100 kHz to 6 MHz and an excellent in-band phase noise tracking performance.
A new frequency synthesizer based on all digital phase-locked loop is proposed to realize the phase noise tracking compensation and reduce the complexity of the all digital phase-locked loop.It uses an digital phasefrequency detector and a nonlinear phase/frequency decision circuit as well as a digitally-controlled oscillator with a low complexity to significantly reduces the hardware complexity.At the same time,the proposed architecture can achieve good noise tracking and fast phase/frequency acquisition and high frequency resolution(approximately 6 kHz) and large linear frequency tuning range.The experimental results show that the proposed frequency synthesizer can achieve a programmable loop bandwidth from 100 kHz to 6 MHz and an excellent in-band phase noise tracking performance.
引文
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[2]Chung C C,Lee C Y.An All-Digital Phase-Locked Loop for HighSpeed Clock Generation[J].IEEE Journal of Solid-State Circuits,2003,38(2):347-351.
[3]Xiu L,Li W,Meiners J,et al.A Novel All-Digital PLL with Software Adaptive Filter[J].IEEE Journal of Solid-State Circuits,2004,39(3):476-483.
[4]Staszewski R B,Balsara P T.Phase-Domain All-Digital Phaselocked Loop[J].IEEE Transactions on Circuits and Systems-Ⅱ:Express Briefs,2005,52(3):159-163.
[5]Calbaza D E,Cordos I,Seth-Smith N,et al.An ADPLL Circuit Using a DDPS for Genlock Applications[C]//International Symposium on Circuits and Systems,2004.
[6]Dalt N D,Thaller E,Gregorius P,et al.A Low Jitter Triple-Band Digital LC PLL in 130 nm CMOS[C]//30th European Solid-State Circuit Conference,2004.
[7]Liu Y,Yum T Y,Xue Q,et al.A 50-m W/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface with Digital Eye-Tracking[J].IEEE Journal of Solid-State Circuits,2004,39(4):613-621.
[8]Liu X,Feng P,Wu N.Low Power Low Phase Noise Phase Locked Loop Frequency Synthesizer with Fast Locking Mode for 2.4 GHz Applications[J].Japanese Journal of Applied Physics,2014,53(53):853-871.
[9]Casha O,Grech I,Badets F.Analysis of the Spur Characteristics of Edge-Combining DLL Based Frequency Multipliers[J].IEEE Transactions on Circuits and SystemsⅡ,2009,56(2):132-136.
[10]肖帅,孙建波,耿华,等.基于FPGA实现的可变模全数字锁相环[J].电工技术学报,2012,27(4):153-158.
[11]Moorthi S,Meganathan D,Janarthanan D,et al.Low Jitter ADPLL Based Clock Generator for High Speed So C Applications[J].International Journal of Electronics,2009,96(11):1183-1189.
[12]张志文,曾志兵,罗隆福,等.基于新型全数字锁相环的同步倍频技术[J].电力自动化备,2010,30(2):123-126,130.