一种适用于FinFET单存储单元的高效的动态故障测试算法
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摘要
FinFET作为现在最前沿的晶体管技术,在嵌入式存储器上得到了广泛应用.但是,新的工艺也带来了新的缺陷.Synopsys公司通过故障建模及测试发现:FinFET存储器比平面存储器对动态故障更敏感.而经典的测试算法仅仅针对静态故障.目前关于动态故障的测试算法极少,并且复杂度很高.因此,本文提出了一种改进的动态故障测试算法,该算法能够覆盖所有连续两次敏化操作的单单元动态故障.
FinFET as the most advanced transistor technology, has been widely used in embedded memory. However, the new process also brings new defects. Synopsys found through fault modeling and testing that FinFET memory is more sensitive to dynamic faults than planar memory. The classic test algorithm is only for static faults. At present, there are few test algorithms for dynamic faults, and the complexity is very high. Therefore, an improved dynamic fault test algorithm is proposed in this paper. This algorithm can cover all single-cell dynamic faults in two successive sensitization operations.
FinFET as the most advanced transistor technology, has been widely used in embedded memory. However, the new process also brings new defects. Synopsys found through fault modeling and testing that FinFET memory is more sensitive to dynamic faults than planar memory. The classic test algorithm is only for static faults. At present, there are few test algorithms for dynamic faults, and the complexity is very high. Therefore, an improved dynamic fault test algorithm is proposed in this paper. This algorithm can cover all single-cell dynamic faults in two successive sensitization operations.
引文
[1] HARUTYUNYAN G, TSHAGHARYAN G, VARDANIAN V, et al. Fault modeling and test algorithm creation strategy for FinFET-based memories[C]//Vlsi Test Symposium. IEEE, 2014:1-6.
[2] HAMDIOUI S, Al-ARS Z, GOOR A J V D. Testing Static and Dynamic Faults in Random Access Memories[C]// IEEE Vlsi Test Symposium. IEEE Computer Society, 2002:395.
[3] BENSO A, BOSIO A, CARLO S D, et al. Automatic March tests generation for static and dynamic faults in SRAMs[C]//Test Symposium, 2005. European. IEEE, 2005:122-127.
[4] HARUTUNYAN G, VARDANIAN V A, ZORIAN Y. Minimal March Tests for Detection of Dynamic Faults in Random Access Memories [J]. Journal of Electronic Testing, 2007, 23(1):55-74.
[5] DU L, ZHAO H, YANG W, et al. Optimization of STI oxide recess uniformity for FinFET beyond 20nm[C]// Semiconductor Technology International Conference. IEEE, 2015:1-4.
[6] JOSEPH J, PATRIKAR R. Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET[M]//VLSI Design and Test. Springer Berlin Heidelberg, 2013:153-159.
[7] HARTYUNYAN G, SHOUKOURIAN S, VARDANIAN V, et al. Extending fault periodicity table for testing faults in memories under 20nm[C]//IEEE East-West Design& Test Symposium. IEEE, 2015:1-4.
[8] HAMDIOUI S, GAYDADJIEV G N, GOOR A J V. A Fault Primitive Based Analysis of Dynamic Memory Faults[C]//IEEE 14 Annual Workshop on Circuits, Systems and Signal Processing. Veldhoven, Netherlands. IEEE, 2003:84-89.
[9] 石磊, 王小力. 一种基于存储器故障原语的March测试算法研究[J]. 微电子学, 2009, 39(2):251-255.
[10] MARINESCU M. Simple and Efficient Algorithms for Functional RAM Testing[C]//International Test Conference 1982, Philadelphia, Pa, USA. DBLP, 1982:236-239.
[11] BOSIO A, DILILLO L, GIRARD P, et al. Advanced Test Methods for SRAMs [M]. Springer US, 2010.
[2] HAMDIOUI S, Al-ARS Z, GOOR A J V D. Testing Static and Dynamic Faults in Random Access Memories[C]// IEEE Vlsi Test Symposium. IEEE Computer Society, 2002:395.
[3] BENSO A, BOSIO A, CARLO S D, et al. Automatic March tests generation for static and dynamic faults in SRAMs[C]//Test Symposium, 2005. European. IEEE, 2005:122-127.
[4] HARUTUNYAN G, VARDANIAN V A, ZORIAN Y. Minimal March Tests for Detection of Dynamic Faults in Random Access Memories [J]. Journal of Electronic Testing, 2007, 23(1):55-74.
[5] DU L, ZHAO H, YANG W, et al. Optimization of STI oxide recess uniformity for FinFET beyond 20nm[C]// Semiconductor Technology International Conference. IEEE, 2015:1-4.
[6] JOSEPH J, PATRIKAR R. Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET[M]//VLSI Design and Test. Springer Berlin Heidelberg, 2013:153-159.
[7] HARTYUNYAN G, SHOUKOURIAN S, VARDANIAN V, et al. Extending fault periodicity table for testing faults in memories under 20nm[C]//IEEE East-West Design& Test Symposium. IEEE, 2015:1-4.
[8] HAMDIOUI S, GAYDADJIEV G N, GOOR A J V. A Fault Primitive Based Analysis of Dynamic Memory Faults[C]//IEEE 14 Annual Workshop on Circuits, Systems and Signal Processing. Veldhoven, Netherlands. IEEE, 2003:84-89.
[9] 石磊, 王小力. 一种基于存储器故障原语的March测试算法研究[J]. 微电子学, 2009, 39(2):251-255.
[10] MARINESCU M. Simple and Efficient Algorithms for Functional RAM Testing[C]//International Test Conference 1982, Philadelphia, Pa, USA. DBLP, 1982:236-239.
[11] BOSIO A, DILILLO L, GIRARD P, et al. Advanced Test Methods for SRAMs [M]. Springer US, 2010.