结合晶体管版图效应分析的模拟集成电路设计
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摘要
为了实现模拟集成电路版图设计的自动化,提出一种称为金属-氧化物-半导体场效应晶体管阵列的版图布局方法。90 nm/1. 2 V互补式MOS的测试元件组(TEG)芯片被开发用以实验采样,芯片搭载多种导电沟道分割形式的多指栅晶体管,晶体管在电路的版图设计中以不同的布局形态呈现。这些晶体管的电气参数被测试并抽取,用以分析和评价其直流性能。以二级模拟运算放大器为实验电路,分别采用晶体管阵列和全定制方式进行版图设计,从工艺波动性和版图面积两方面进行对比。成品实测结果表明:以晶体管阵列方式实现共源共栅运放电路时,10枚TEG芯片的平均失调电压为4. 48 m V,对比手工版图的5. 59 m V,抗波动性能约提升了20%,显示了晶体管阵列版图设计方法的有效性。
To realize layout design automation for an analog integrated circuit( IC),the layout design methodology called metal-oxide-semiconductor field-effect transistor( MOSFET) array was proposed in this paper. A 90 nm/1. 2 V complementary MOS testing elements group( TEG) chip was manufactured for collecting the sampling data. The multi-finger gate MOS transistors based on various channel decompositions manner were implemented in this chip,and the transistors ware presented in different placement patterns in circuit layout design. The electrical parameters were measured and extracted,so the direct current( DC)characteristics were analyzed and evaluated. Meanwhile,taking a two-stage operating amplifier as the design case,the transistor array layout and full-custom layout were employed for layout design. The performance analysis and comparison in terms of process variation and layout area were taken. The measurement results show that in case of the cascade operating amplifier with transistor array( TA) style,the average value of offset voltages among 10 of TEG chips is 4. 48 m V. Compared to 5. 59 m V measured from custom layout,about 20% improvement of performance in aspect of process variation-tolerance is obtained,which shows the effectiveness of TA layout structure for analog circuits.
To realize layout design automation for an analog integrated circuit( IC),the layout design methodology called metal-oxide-semiconductor field-effect transistor( MOSFET) array was proposed in this paper. A 90 nm/1. 2 V complementary MOS testing elements group( TEG) chip was manufactured for collecting the sampling data. The multi-finger gate MOS transistors based on various channel decompositions manner were implemented in this chip,and the transistors ware presented in different placement patterns in circuit layout design. The electrical parameters were measured and extracted,so the direct current( DC)characteristics were analyzed and evaluated. Meanwhile,taking a two-stage operating amplifier as the design case,the transistor array layout and full-custom layout were employed for layout design. The performance analysis and comparison in terms of process variation and layout area were taken. The measurement results show that in case of the cascade operating amplifier with transistor array( TA) style,the average value of offset voltages among 10 of TEG chips is 4. 48 m V. Compared to 5. 59 m V measured from custom layout,about 20% improvement of performance in aspect of process variation-tolerance is obtained,which shows the effectiveness of TA layout structure for analog circuits.
引文
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[2]TALLARICO A N,REGGIANI S,DEPETRO R,et al.Hot-carrier degradation in power LDMOS:selective LOCOS-versus STI-based architecture[J].IEEE journal of the electron devices society,2018,6(1):219-226.
[3]周帅,刘成国,唐晓.基于射频功率放大器的阻抗匹配技术[J].河南科技大学学报(自然科学版),2018,39(5):94-99,104.
[4]李建伟,董刚,杨银堂,等.考虑工艺波动影响的RLC互连统计延时[J].电子与信息学报,2009,31(11):2767-2771.
[5]张瑛,WANG J M,肖亮,等.工艺参数随机扰动下的传输线建模与分析新方法[J].电子学报,2005,33(11):1959-1964.
[6]LIU B,YANG B,NAKATAKE S.Layout-aware variability characterization of CMOS current sources[J].IEICE transactions on electronics,2012,95(4):696-705.
[7]CHEN G,FUJIMURA T,DONG Q,et al.DC characteristics and variability on 90 nm CMOS transistor array-style analog layout[J].ACM transactions on design automation of electronic systems,2016,21(3):1-21.
[8]LIN P H,CHANG Y W,HUNG C M.Recent research development and new challenges in analog layout synthesis[C]//Proceedings of 21st Asia and South Pacific Design Automation Conference,2016.Macao:IEEE,2016.
[9]SOARES C F T,PETRAGLA A.Automatic placement to improve capacitance matching using a generalized commoncentroid layout and spatial correlation optimization[J].IEEE transactions on CAD of integrated circuits and systems,2015,34(10):1691-1695.
[10]LINM P H,CHANG P H,LEE S Y,et al.De MixGen:deterministic mixed-signal layout generation with separated analog and digital signal paths[J].IEEE transactions on CAD of integrated circuits and systems,2016,35(8):1229-1242.
[11]NAKATAKE S,KAWAKITA M,ITO T,et al.Regularity-oriented analog placement with conditional design rules[J].IEICE transactions on fundamentals of electronics communication and computer sciences,2010,93(12):2389-2398.
[12]YANG B,DONG Q,LI J,et al.Structured analog circuit design and MOS transistor decomposition for high accuracy applications[C]//ICCAD-IEEE ACM International Conference on Computer-Aided Design.San Jose:IEEE,2010.
[13]LIU B,CHEN G,YANG B,et al.Routable and matched layout styles for analog module generation[J].ACM transactions on design automation of electronic systems,2018,23(4):1-17.
[14]PELGROM M J M,DUINMAIJER A C J,WELBERS A P G.Matching properties of MOS transistors[J].IEEE journal of solid-state circuits,1989,24(5):1433-1440.
[15]HASTINGS A.The art of analog layout[M].Englewood:Prentice Hall,2006.