一种低功耗的双尾电流动态比较器
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摘要
提出了一种新型技术来降低动态比较器的功耗。预放大器的输出直接与锁存节点连接。在没有明显增大锁存节点负载电容的基础上,在隐藏的静态电流通路上设计2个开关晶体管来避免静态功耗,实现了低功耗。基于TSMC 0.18μm CMOS工艺,对提出的比较器进行仿真,并与其他三种比较器进行对比。仿真结果表明,在1.8V供电电压、频率为100 MHz、共模电压为0.9V的条件下,该比较器的功耗为26.13μW,相比传统双尾动态比较器,功耗降低了49%。延时为219ps,失调电压为6.3mV。该比较器适用于低功耗设计领域。
A new technique of double-tail current comparator was proposed to reduce the power consumption of dynamic comparators.The pre-amplifier outputs were directly connected to the latching nodes,and it didn't increase the load capacitance of the latching nodes.Two switches were designed to cutoff the hidden static current path,which achieved low power.The proposed structure and the previous double-tail current dynamic comparators had been simulated in TSMC 0.18μm CMOS technology.Simulation results showed that,under the conditions of 1.8 V supply voltage,100 MHz clock frequency and 0.9 Vinput common mode voltage,the power consumption was reduced by 49%compared with the conventional comparators.The proposed comparator achieved an offset voltage of 6.3 mV and a delay of 219 ps.The proposed double-tail current comparator was suitable for low power applications.
A new technique of double-tail current comparator was proposed to reduce the power consumption of dynamic comparators.The pre-amplifier outputs were directly connected to the latching nodes,and it didn't increase the load capacitance of the latching nodes.Two switches were designed to cutoff the hidden static current path,which achieved low power.The proposed structure and the previous double-tail current dynamic comparators had been simulated in TSMC 0.18μm CMOS technology.Simulation results showed that,under the conditions of 1.8 V supply voltage,100 MHz clock frequency and 0.9 Vinput common mode voltage,the power consumption was reduced by 49%compared with the conventional comparators.The proposed comparator achieved an offset voltage of 6.3 mV and a delay of 219 ps.The proposed double-tail current comparator was suitable for low power applications.
引文
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[2] SCHINKEL D,MENSINK E,KLUMPERINK E,et al.A double-tail latch-type voltage sense amplifier with 18ps setup+hold time[C]∥IEEE ISSCC.San Francisco,CA,USA.2007:314-315,605.
[3] GAO J,LI G,LI Q.High-speed low-power commonmode insensitive dynamic comparator[J].Elec Lett,2015,51(2):134-136.
[4] ABBAS M,FURUKAWA Y,KOMATSU S,et al.Clocked comparator for high-speed applications in65nm technology[C]∥IEEE Asian Sol Sta Circ Conf.San Francisco,CA,USA.2010:1-4.
[5] CHEN L,SANYAL A,MA J,et al.Comparator common-mode variation effects analysis and its application in SAR ADCs[C]∥IEEE Int Symp Circ&Syst.Montreal,Canada.2016:2014-2017.
[6] XU D,XU S,CHEN G.High-speed low-power and low-power supply voltage dynamic comparator[J].Elec Lett,2015,51(23):1914-1916.
[7]MATTHEWS T W,HEEDLEY P L.A simulation method for accurately determining DC and dynamic offsets in comparators[C]∥48th Midwest Symp Circ&Syst. Covington, KY, USA.2005,2:1815-1818.
[8] BABAYAN-MASHHADI S,LOTFI R.Analysis and design ofalow-voltagelow-powerdouble-tail comparator[J].IEEE Trans Very Large Scale Integr Syst,2014,22(2):343-352.
[9] HE J,ZHAN S,CHEN D,et al.Analyses of static and dynamic random offset voltages in dynamic comparators[J].IEEE Trans Circ&Syst I:Regu Pap,2009,56(5):911-919.
[10]KHALIL K,ABBAS M,ABDELGAWAD M.Novel technique for reducing the comparator delay dispersion in 45nm CMOS technology for level-crossing ADCs[C]∥ISCDG.Grenoble,France.2012:21-24.