MLC型NAND闪存中Polar码的优化设计
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摘要
为了进一步提升多级存储单元的纠错性能,提出了一种基于多级存储单元阈值电压分布的Polar码优化设计方法。针对多级存储单元的固有特性,该方法迭代计算各存储单元比特的巴氏参数值优化设计Polar码。分析了不同构造方法对多级存储单元闪存性能的影响,并与文中所构造的Polar码和系统Polar码在多级存储单元信道中的性能进行了比较。仿真结果表明:在多级存储单元信道中,当误码率为10~(-5)时,本文所构造的Polar码与高斯信道下经典巴氏参数法构造的Polar码相比可获得约2 d B增益;当信噪比为21 d B时,与蒙特卡罗法构造的Polar码相比,文中设计的系统Polar码的误码率可提升2个数量级。
To further improve the error correction performance of the multi-level cell( MLC) flash memory,an optimal design method for Polar codes based on the threshold voltage distribution of MLC is proposed. Aimed at the inherent characteristics of MLC flash memory channel,the method can optimize polar codes by iteratively calculating the Bhattacharyya parameter of each memory cell. The influences of different construction methods on the performance of MLC flash memory are analyzed and compared with the Polar code and the systematic Polar code constructed in this paper. Simulation results show that the proposed Polar code outperforms the performance of the Polar code constructed by traditional Bhattacharyya parameter method in the Gaussian channel about 2 d B gain at the bit error rate( BER) of 10-5 in MLC flash memory channel. The systematic Polar code can improve BER performance by 2 order of magnitudes compared with the Polar code constructed by Monte-Carlo method when the signal-to-noise rate( SNR) is21 d B.
To further improve the error correction performance of the multi-level cell( MLC) flash memory,an optimal design method for Polar codes based on the threshold voltage distribution of MLC is proposed. Aimed at the inherent characteristics of MLC flash memory channel,the method can optimize polar codes by iteratively calculating the Bhattacharyya parameter of each memory cell. The influences of different construction methods on the performance of MLC flash memory are analyzed and compared with the Polar code and the systematic Polar code constructed in this paper. Simulation results show that the proposed Polar code outperforms the performance of the Polar code constructed by traditional Bhattacharyya parameter method in the Gaussian channel about 2 d B gain at the bit error rate( BER) of 10-5 in MLC flash memory channel. The systematic Polar code can improve BER performance by 2 order of magnitudes compared with the Polar code constructed by Monte-Carlo method when the signal-to-noise rate( SNR) is21 d B.
引文
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[8]ARIKAN E.Channel polarization:a method for constructing capacity-achieving codes for symmetric binary-input memoryless channels[J].IEEE Transactions on Information Theory,2009,55(7):3051-3073.
[9]ATWOOD G,FAZIO A,MILLS D,et al.Intel strata flash memory technology overview[J].Intel Technology Journal,1997,4:1-8.
[10]ARIKAN E.Channel combining and splitting for cutoff rate improvement[J].IEEE Transactions on Information Theory,2006,52(2):628-639.
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[12]PAMUK A.An FPGA implementation architecture for decoding of polar codes[C]//Proceedings of the International Symposium on Wireless Communication Systems.Piscataway:IEEE Press,2011:437-444.
[13]LI H J,YUAN J H.A practical construction method for polar codes in AWGN channels[C]//Proceedings of the TENCON Spring Conference.Piscataway:IEEE Press,2013:223-226.
[14]ARIKAN E.A performance comparison of polar codes and Reed-Muller codes[J].IEEE Communications Letters,2008,12(6):447-449.
[15]TAL I,VARDY A.How to construct polar codes[J].IEEE Transactions on Information Theory,2013,59(10):6562-6582.
[2]FEI Z S,YUAN J H,XIAO M,et al.Recent development of error control codes for future communication and storage systems[J].China Communications,2017,14(8):iii-v.
[3]CHEN B N,ZHANG X M,WANG Z F.Error correction for multi-level NAND flash memory using reed-solomon codes[C]//Proceedings of the Workshop on Signal Processing Systems.Piscataway:IEEE Press,2008:94-99.
[4]CHOI H,LIU W,SUNG W.VLSI implementation of BCHerror correction for multilevel cell NAND flash memory[J].IEEE Transactions on VLSI,2010,18(5):843-847.
[5]张旋,慕建君,焦晓鹏.一种MLC闪存存储系统的比特翻转译码算法[J].西安电子科技大学学报(自然科学版),2017,44(5):75-80.ZHANG Xuan,MU Jianjun,JIAO Xiaopeng.Bit-flipping decoding algorithm for the MLC flash memory[J].Journal of Xidian University(Natural Science Edition),2017,44(5):75-80.(in Chinese)
[6]LI Y,ALHUSSIEN H,HARATSCH E F,et al.A study of polar codes for MLC NAND flash memories[C]//Proceedings of the International Conference on Computing,Networking and Communications.Piscataway:IEEE Press,2015:608-612.
[7]SONG H C,ZHANG C,ZHANG S Q,et al.Polar codebased error correction code scheme for NAND flash memory applications[C]//Proceedings of the International Conference on Wireless Communications&Signal Processing.Piscataway:IEEE Press,2016:1-5.
[8]ARIKAN E.Channel polarization:a method for constructing capacity-achieving codes for symmetric binary-input memoryless channels[J].IEEE Transactions on Information Theory,2009,55(7):3051-3073.
[9]ATWOOD G,FAZIO A,MILLS D,et al.Intel strata flash memory technology overview[J].Intel Technology Journal,1997,4:1-8.
[10]ARIKAN E.Channel combining and splitting for cutoff rate improvement[J].IEEE Transactions on Information Theory,2006,52(2):628-639.
[11]ARIKAN E.Systematic polar coding[J].IEEE Communications Letters,2011,15(8):860-862.
[12]PAMUK A.An FPGA implementation architecture for decoding of polar codes[C]//Proceedings of the International Symposium on Wireless Communication Systems.Piscataway:IEEE Press,2011:437-444.
[13]LI H J,YUAN J H.A practical construction method for polar codes in AWGN channels[C]//Proceedings of the TENCON Spring Conference.Piscataway:IEEE Press,2013:223-226.
[14]ARIKAN E.A performance comparison of polar codes and Reed-Muller codes[J].IEEE Communications Letters,2008,12(6):447-449.
[15]TAL I,VARDY A.How to construct polar codes[J].IEEE Transactions on Information Theory,2013,59(10):6562-6582.