NLFM脉冲压缩及其FPGA时域实现
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摘要
介绍非线性调频(NLFM)信号的产生原理和设计匹配滤波器实现脉冲压缩技术的方法.使用MATLAB工具产生NLFM脉冲及雷达回波信号,基于FPGA器件EP2C35F672C8设计分布式FIR结构的匹配滤波器,实现脉冲压缩技术,对采样、量化后的回波信号进行脉冲压缩处理,最后使用Modelsim对脉冲压缩后的回波信号进行波形仿真,检测匹配滤波器的设计效果.整个电路设计采用全流水线并行执行的结构,占用硬件资源:2 468个逻辑单元、2 073个寄存器、25 KB的RAM.利用FPGA芯片丰富的BRAM和LAB代替乘法器IP,打破硬件资源对滤波器长度的限制.
The generation principle of nonlinear frequency modulated( NLFM) signal and the method of design matched filter realized pulse compression technique were analyzed in this paper. NLFM signal and the radar echo signal were generated by MATLAB tools,distributed FIR structure for realizing pulse compression technology was designed based on FPGA device EP2 C35 F672 C8,which processed the sampled and quantized echo signals finally. The simulated waveform of the signal which was handled by Modelsim software to detect the effect of the matched filter. The whole circuit of the filter was designed by using the structure of full pipelined parallel execution. The FPGA hardware resources that the circuit occupied include 2 468 logical units,2 073 registers,and 25 KB of RAM. By using BRAM and LAB of the FPGA chip instead of the multipliers IP,the limitation of hardware resources on the length of the filter was broken.
The generation principle of nonlinear frequency modulated( NLFM) signal and the method of design matched filter realized pulse compression technique were analyzed in this paper. NLFM signal and the radar echo signal were generated by MATLAB tools,distributed FIR structure for realizing pulse compression technology was designed based on FPGA device EP2 C35 F672 C8,which processed the sampled and quantized echo signals finally. The simulated waveform of the signal which was handled by Modelsim software to detect the effect of the matched filter. The whole circuit of the filter was designed by using the structure of full pipelined parallel execution. The FPGA hardware resources that the circuit occupied include 2 468 logical units,2 073 registers,and 25 KB of RAM. By using BRAM and LAB of the FPGA chip instead of the multipliers IP,the limitation of hardware resources on the length of the filter was broken.
引文
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[2]梁丽.基于FPGA的雷达信号处理系统设计[D].南京:南京理工大学,2006.
[3]阮黎婷.非线性调频信号的波形设计与脉冲压缩[D].西安:西安电子科技大学,2009.
[4]汪堃.基于FPGA的脉冲压缩系统研究与实现[D].武汉:华中科技大学,2009.
[5]程远东,郑晶翔.一种用于数字下变频的高阶分布式FIR滤波器及FPGA实现[J].电子技术应用,2011,37(2):57-59.
[6]李书华,曾以成.基于分布式算法的高阶FIR滤波器及其FPGA实现[J].计算机工程与应用,2010,46(12):136-138.
[7]徐飞.基于FPGA的非线性调频信号脉冲压缩的实现[D].西安:西安电子科技大学,2014.
[8]孙宝鹏.基于FPGA的雷达信号处理算法设计与实现[D].北京:北京理工大学,2014.
[9]崔永强,高晓丁,贺素馨.基于FPGA分布式算法的滤波器设[J].现代电子技术,2010,33(16):117-119.
[10]杨维明.一种基于EPLD技术的信号取模方法[J].湖北大学学报(自然科学版),1999,11(2):138-141.
[11]杜勇.数字滤波器的MATLAB与FPGA实现[M].2版.北京:电子工业出版社,2015.