面阵探测器KAI-04022成像系统设计
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摘要
介绍了一种基于行间转移CCD KAI-04022的成像系统设计方法。成像系统采用灵活的驱动电路设计方法,利用二极管钳位及MOSFET驱动器完成了各个两电平驱动信号的设计,利用模拟前端芯片和压摆率控制电路产生垂直三电平驱动信号。模拟前端芯片AD9920A自带12位精度的A/D转换器,CCD输出的模拟信号通过它进行数字化采样,数字化的图像信号将被FPGA读入到下一级处理模块。为了解决双通道输出产生的非均匀性问题,本系统采用多点校正算法,设计了可实现的FPGA硬件校正模块,在代价较小的情况下,完成了非均匀校正功能。校正后的图像利用高速LVDS接口传输给上位机。实验证明,在像素时钟为40MHz时,成像系统的帧频可以达到16frame/s。在实验室环境下,对CCD直接进行辐照测试实验,测得图像的信噪比为33d B,成像质量满足系统的要求。
A design method for area array-CCD KAI-04022 imaging system based on FPGA was proposed. A flexible method of the driving circuit was used to design the imaging system. The two level driving signal was generated by the diode clamp circuit and a MOSFET driver. The three level driving signal was generated by the AFE chip and slew rate control circuit. A 12 bit ADC was embedded in the AD9920 A, through which the output analog signal from CCD converted to the digital signal. The digital image signal would be stored into the next level processing unit by FPGA. The multipoint correction algorithm was adopted to solve the non-uniformity resulting from the dual output channel. A realizable FPGA hardware correction unit was designed. The non-uniformity correction was accomplished under low cost. The corrected image was transmitted to PC by the interface bus of high speed LVDS. The experimental results indicated that the max frame rate of the imaging system was 16f/s, when the pixel rate was 40 MHz.The signal-to-noise ratio of the image captured in the laboratory was 33 d B and the image quality would meet the requirements of the system.
A design method for area array-CCD KAI-04022 imaging system based on FPGA was proposed. A flexible method of the driving circuit was used to design the imaging system. The two level driving signal was generated by the diode clamp circuit and a MOSFET driver. The three level driving signal was generated by the AFE chip and slew rate control circuit. A 12 bit ADC was embedded in the AD9920 A, through which the output analog signal from CCD converted to the digital signal. The digital image signal would be stored into the next level processing unit by FPGA. The multipoint correction algorithm was adopted to solve the non-uniformity resulting from the dual output channel. A realizable FPGA hardware correction unit was designed. The non-uniformity correction was accomplished under low cost. The corrected image was transmitted to PC by the interface bus of high speed LVDS. The experimental results indicated that the max frame rate of the imaging system was 16f/s, when the pixel rate was 40 MHz.The signal-to-noise ratio of the image captured in the laboratory was 33 d B and the image quality would meet the requirements of the system.
引文
[1]胡渝,荣健.CCD的发展现状及展望[J].仪器仪表学报,2005,26(8):718-720.
[2]王庆有.CCD应用技术[M].天津:天津大学出版社,2 000.
[3]刘金国,余达,周怀得,等.面阵CCD芯片KAI21010M的高速驱动系统设计[J].光学精密工程,2008,16(9):1622-1628
[4]张贵祥,金光,郑亮亮,等.高速多通道CCD图像数据处理与传输系统设计[J].液晶与显,2011,26(3):397-403.
[5]盛翠霞,张涛,纪晶,等.高分辨率CCD芯片FTF4052M的驱动系统设计[J].光学精密工程,2007,15(4):564-569.
[6]陶明慧,张星祥,张宇,等.KAI-2093型面阵CCD多模式驱动时序设计[J].液晶与显示,2011,26(1):105-110.
[7]程万胜,赵杰,蔡鹤皋,CCD像素响应非均匀的校正方法[J]光学精密工程,2008,16(2):314-318.
[8]许秀贞,李自田,薛利军.CCD噪声分析及处理技术[J].红外与激光工程,2004,33(4):343-347.
[2]王庆有.CCD应用技术[M].天津:天津大学出版社,2 000.
[3]刘金国,余达,周怀得,等.面阵CCD芯片KAI21010M的高速驱动系统设计[J].光学精密工程,2008,16(9):1622-1628
[4]张贵祥,金光,郑亮亮,等.高速多通道CCD图像数据处理与传输系统设计[J].液晶与显,2011,26(3):397-403.
[5]盛翠霞,张涛,纪晶,等.高分辨率CCD芯片FTF4052M的驱动系统设计[J].光学精密工程,2007,15(4):564-569.
[6]陶明慧,张星祥,张宇,等.KAI-2093型面阵CCD多模式驱动时序设计[J].液晶与显示,2011,26(1):105-110.
[7]程万胜,赵杰,蔡鹤皋,CCD像素响应非均匀的校正方法[J]光学精密工程,2008,16(2):314-318.
[8]许秀贞,李自田,薛利军.CCD噪声分析及处理技术[J].红外与激光工程,2004,33(4):343-347.