一种转换时间可范围控制的MLVDS驱动器
|
摘要
为实现多芯片间的高速数据传输,设计了一款应用于多点总线系统的多点低压差分信号(Multi-point Low Voltage Differential Signaling,MLVDS)驱动器,其转换时间可被控制在一定范围内。该驱动器主电路采用互补桥式开关管结构将TTL信号转换成CMOS差分电压信号。这种结构能削弱衬底偏置效应所带来的输出波形失真。预驱动电路采用对电容恒流充放电电路结构改变信号的压摆率。在输出级通过添加两个泄流二极管来平衡信号的过冲,从而保证了信号的完整性。芯片采用GSMC 0.18μm1P4M的CMOS工艺实现,测试结果表明工作频率为125 MHz时输出信号幅值为550 mV,上升时间为1.190 ns,下降时间为1.159 ns,满足TIA/EIA-899协议的要求。
In order to realize the high speed data transmission between multi-chips, a Multi-point Low Voltage Differential Signaling(MLVDS)driver for multi-point bus system is presented, which makes the transition-time controlled in a certain range. The main structure of driver consisting of complementary bridge switches can transfer TTL signals to CMOS voltage signals. This structure is proposed to weaken the output waveform distortion caused by substrate bias effect. The pre-drive circuit with constant current charge-discharge circuit structure is used to change the signal slew rate.Meanwhile, by adding two clamping diodes to balance the signals in the output level, signal integrity is ensured. The MLVDS driver is implemented in GSMC 0.18 μm 1P4M CMOS process. The measurement results show that the differential output amplitude is 550 mV and the rising time is 1.190 ns as well as the falling time goes to 1.159 ns when the frequency is 125 MHz, which meets the application requirement of the protocol TIA/EIA-899.
In order to realize the high speed data transmission between multi-chips, a Multi-point Low Voltage Differential Signaling(MLVDS)driver for multi-point bus system is presented, which makes the transition-time controlled in a certain range. The main structure of driver consisting of complementary bridge switches can transfer TTL signals to CMOS voltage signals. This structure is proposed to weaken the output waveform distortion caused by substrate bias effect. The pre-drive circuit with constant current charge-discharge circuit structure is used to change the signal slew rate.Meanwhile, by adding two clamping diodes to balance the signals in the output level, signal integrity is ensured. The MLVDS driver is implemented in GSMC 0.18 μm 1P4M CMOS process. The measurement results show that the differential output amplitude is 550 mV and the rising time is 1.190 ns as well as the falling time goes to 1.159 ns when the frequency is 125 MHz, which meets the application requirement of the protocol TIA/EIA-899.
引文
[1]张旭光.高速LVDS接口电路关键技术的研究[D].长沙:国防科技大学,2012.
[2]刘祥元,陈书明.LVDS高速在I/O接口单元的设计研究[J].计算机工程与科学,2001.
[3]Dietz J.Introduction to M-LVDS(TIA/EIA-899)[R].[S.l.]:Texas Instruments,2002.
[4]Multipoint-LVDS line driver and receiver[R].[S.l.]:Texas Instruments,2003.
[5]M-LVDS signaling rate versus distance[R].[S.l.]:Texas Instruments,2003.
[6]Mulcahy D.M-LVDS for true multipoint interfaces on buses and more[R].[S.l.]:Texas Instruments,2009.
[7]Dehmelt F.Transmission at 200 Mbps in VME card cage using LVDM[R].[S.l.]:Texas Instruments,2002.
[8]Glisic D.An introduction to M-LVDS and clock and data distribution applications[R].[S.l.]:National Semiconductor,2008.
[9]Telecommunications Industry Association.TIA/EIA-899 Electrical characteristics of multi-point low voltage differential signaling interface circuits[S].2002.
[10]刘正,游轶雄,王健,等.CMOS线驱动器输出信号压摆率控制的研究[J].微电子学,2003,33(4).
[11]Telecommunications Industry Association.TIA/EIA-644-A Electrical characteristics of low voltage differential signaling interface circuits[S].2001.
[12]谭炜锋.高速LVDS发送器设计[D].成都:电子科技大学,2009.
[13]Tajalli A,Leblebici Y.A slew controlled LVDS output driver circuit in 0.18μm CMOS technology[J].IEEE Journal of Solid-State Circuits,2009,44(2).
[14]Razavi B.Design of analog CMOS and integrated circuit[M].[S.l.]:Mc Graw-Hill Company,Inc,2001.
[15]Gingerich K.Interoperability of M-LVDS and Bus-LVDS[R].2003.
[16]Nilsson J W,Riedel S A.Electric circuits[M].北京:电子工业出版社,2011.
[2]刘祥元,陈书明.LVDS高速在I/O接口单元的设计研究[J].计算机工程与科学,2001.
[3]Dietz J.Introduction to M-LVDS(TIA/EIA-899)[R].[S.l.]:Texas Instruments,2002.
[4]Multipoint-LVDS line driver and receiver[R].[S.l.]:Texas Instruments,2003.
[5]M-LVDS signaling rate versus distance[R].[S.l.]:Texas Instruments,2003.
[6]Mulcahy D.M-LVDS for true multipoint interfaces on buses and more[R].[S.l.]:Texas Instruments,2009.
[7]Dehmelt F.Transmission at 200 Mbps in VME card cage using LVDM[R].[S.l.]:Texas Instruments,2002.
[8]Glisic D.An introduction to M-LVDS and clock and data distribution applications[R].[S.l.]:National Semiconductor,2008.
[9]Telecommunications Industry Association.TIA/EIA-899 Electrical characteristics of multi-point low voltage differential signaling interface circuits[S].2002.
[10]刘正,游轶雄,王健,等.CMOS线驱动器输出信号压摆率控制的研究[J].微电子学,2003,33(4).
[11]Telecommunications Industry Association.TIA/EIA-644-A Electrical characteristics of low voltage differential signaling interface circuits[S].2001.
[12]谭炜锋.高速LVDS发送器设计[D].成都:电子科技大学,2009.
[13]Tajalli A,Leblebici Y.A slew controlled LVDS output driver circuit in 0.18μm CMOS technology[J].IEEE Journal of Solid-State Circuits,2009,44(2).
[14]Razavi B.Design of analog CMOS and integrated circuit[M].[S.l.]:Mc Graw-Hill Company,Inc,2001.
[15]Gingerich K.Interoperability of M-LVDS and Bus-LVDS[R].2003.
[16]Nilsson J W,Riedel S A.Electric circuits[M].北京:电子工业出版社,2011.