摘要
为解决大多数循环型(cyclic)模数转换器(analog-to-digital convertor, ADC)不能实现双输入模式的问题,提出了一种10位的可实现单端和差分两种输入模式的cyclic ADC结构.采用RSD算法,实现对比较器阈值偏差的修正,提出一种两级自补偿结合增益自举的改进型运放结构,在实现高增益的同时,能够保证输出结果不受环路失调影响.仿真结果表明在5.2 MHz工作时钟和2.5 V电源电压下,提出的cyclic ADC实现了200 ksps的转换速度,信噪比60.98 dB,有效位数9.8 bit,功耗4.97 mW,版图面积0.059 mm2.研究结论表明该电路有较高的转换速度和精度,且由于能够实现单端和差分两种输入模式,使得该电路的适用范围得到了扩展.
In order to solve the problem that most cyclic ADCs can not implement dual input modes, a 10-bit cyclic ADC with single-ended input mode and differential input mode is proposed in this paper. By using RSD algorithm, the threshold deviation of comparators is corrected. And improved operational amplifier structure with two-stage self-compensation and gain boosted is proposed, which can achieve high gain and ensures that the output result is not affected by loop offset. Simulation results show that the proposed cyclic ADC has a conversion speed of 200 ksps under a 5.2 MHz working clock and 2.5 V supply, the signal to noise ratio is 60.98 dB, the effective number of bits is 9.8 bit, the power dissipation is 4.97 m W, and the layout area is 0.059 mm2. The research conclusion indicates that the circuit has relatively high conversion speed and precision, and the applicability of the circuit is extended due to the dual input modes.
引文
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