保温时间对GaAs功率芯片钎缝组织及性能的影响
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  • 英文篇名:Effect of holding time on brazing structure and properties of Ga As power chips
  • 作者:任卫朋 ; 罗燕 ; 刘凯 ; 陈靖 ; 王立春
  • 英文作者:REN Wei-peng;LUO Yan;LIU Kai;CHEN Jing;WANG Li-chun;Shanghai Aerospace Electronic Technology Institute;
  • 关键词:GaAs芯片 ; AuSn20钎料 ; 过渡层 ; 界面反应 ; 组织演变
  • 英文关键词:GaAs chip;;AuSn20 solder;;transition layer;;interfacial reaction;;microstructure evolution
  • 中文刊名:HSJJ
  • 英文刊名:Welding Technology
  • 机构:上海航天电子技术研究所;
  • 出版日期:2019-06-28
  • 出版单位:焊接技术
  • 年:2019
  • 期:v.48;No.317
  • 语种:中文;
  • 页:HSJJ201906005
  • 页数:4
  • CN:06
  • ISSN:12-1070/TG
  • 分类号:5+21-23
摘要
GaAs芯片的使用性能受其散热效果决定,而散热主要依靠散热垫块与芯片连接的钎缝来决定。为增加钎缝的散热效果和基体结合强度,文中分别在芯片层利用物理气相沉积方法沉积Pd和Au膜,而在Cu/Mo/Cu散热垫块上沉积Ni和Au膜,采用AuSn20共晶钎料,研究保温时间对钎焊缝组织和界面结合性能影响。研究结果表明:共晶结构主要由15~20μm厚的合金层和0.5~3μm厚的IMC层构成。随着保温时间延长,合金中Sn元素会逐渐被IMC层消耗,合金成分往富Au的(L+ζ′)相区迁移,相比例增加,保温时间超过60 s后, IMC层厚度超过3.9μm,剪切力快速减小至89.67 N。
        The performance of GaAs chip was determined by its heat dissipation effect, and the heat dissipation mainly depended on the brazing seam between the heat dissipation pad and the chip. In order to increase the heat dissipation effect of the brazing seam and the bonding strength with the matrix, Pd and Au films were deposited on the chip layer by physical vapor deposition, and Ni and Au films were deposited on the Cu/Mo/Cu heat dissipation pad. The AuSn20 eutectic solder was used to study the effect of holding time on the brazed microstructure and interface bonding properties. The results showed that eutectic structure was mainly composed of alloy layer 15~20 μm thick and IMC layer 0.5 ~3 μm thick. As the holding time prolongs, the Sn element in the alloy will gradually be consumed by IMC layer. The alloy composition moved to Au-rich( L + ζ ′) phase region. The proportion ofζ′(Au5 Sn) phase increased. When the holding time exceeded 60 s, the thickness of IMC layer exceeded 3.9 μm,and the shear strength decreased to 90 N rapidly.
引文
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