基于模型和库的处理器伪随机激励生成器设计与实现
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摘要
面对处理器巨大的验证空间,伪随机激励生成器成为处理器研发中必不可少的工具。处理器设计改变尤其是架构和指令集的变化会导致之前的处理器测试集合部分甚至全部失效,验证维护成本巨大。提出一种层次化的、基于模型和库的处理器伪随机激励生成器实现方法,针对处理器设计的特点,基于指令树建模、多维访存地址建模和处理器专家库建模等关键技术重点解决处理器研发中测试集合如何高效重用的难题。实际应用表明,该方法能够很好地适应处理器设计变化,增强处理器激励生成器的易用性和可重用性,测试集合移植重用率可以达到95%以上,显著缩短处理器更新换代时的验证周期。
Processor pseudo-random test generators are important and necessary in processor research and development,which can generate large numbers of tests so as to cover the huge verification space.However,some of tests in the test set may become illegal and useless when the processor design changes,especially when instruction set or architecture changes,resulting in significant verification and maintenance costs.In order to tackle the problem,a hierarchical method based on models and libraries is proposed to create a processor pseudo-random test generator.Several techniques such as instruction set tree modeling,multidimensional memory address modeling and processor professional knowledge library modeling are used to solve the problem of how to efficiently reuse test sets in processor research and development.The practical application shows that this method can well adapt to the changes of processor design and enhance the usability and reusability of processor pseudo-random test generators.The reuse rate of test set can reach more than 95%,which can significantly shorten the verification cycle when the processor design is changed and upgraded.
Processor pseudo-random test generators are important and necessary in processor research and development,which can generate large numbers of tests so as to cover the huge verification space.However,some of tests in the test set may become illegal and useless when the processor design changes,especially when instruction set or architecture changes,resulting in significant verification and maintenance costs.In order to tackle the problem,a hierarchical method based on models and libraries is proposed to create a processor pseudo-random test generator.Several techniques such as instruction set tree modeling,multidimensional memory address modeling and processor professional knowledge library modeling are used to solve the problem of how to efficiently reuse test sets in processor research and development.The practical application shows that this method can well adapt to the changes of processor design and enhance the usability and reusability of processor pseudo-random test generators.The reuse rate of test set can reach more than 95%,which can significantly shorten the verification cycle when the processor design is changed and upgraded.
引文
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[4]Schubert K-D,Roesner W,Ludden J M,et al.Functional verication of the IBM POWER7 microprocessor and POWER7multiprocessor systems[J].IBM Journal of Research.&Development,2011,55(3):10-17.
[5]Zhu Ying,Chen Cheng,Li Yan-zhe,et al.Creation of FPGA verification platform for a high performance multiple-core microprocessor[J].Journal of Computer Research and Development,2014,51(6):1295-1303.(in Chinese)
[6]Ludden J M,Roesner W,Heiling G M,et al.Functional verification of the POWER4microprocessor and POWER4multiprocessor systems[J].IBM Journal of Research.&Development,2002,46(1):53-76.
[7]Wagner I,Bertacco V,Austin T.StressTest:An automatic approach to test generation via activity monitors[C]∥Proc of the 42nd Design Automation Conference,2005:783-788.
[8]Fournier L,Arbetman Y,Levinger M.Functional verification methodology for microprocessors using the genesys test program generator:Application to the x86microprocessors family[C]∥Proc of Design Automation and Test in Europe(DATE 99),1999:434-441.
[9]Aharon A,Dave G,Levinger M,et al.Test program generationfor functional verification of power PC processors in IBM[C]∥Proc of ACM/IEEE 32nd Design Automation Conference,1995:279-285.
[10]Lichtenstein Y,Malka Y,Aharon A.Model-based test generation for processor design verification[C]∥Proc of Innovative Applications of Artificial Intelligence(IAAI),1994:83-94.
[11]Zhang Xin,Huang Kai,Meng Jian-yi,et al.Multi-layer random stimulus strategy for microprocessor verification[J].Application Research of Computers,2010,27(4):1284-1288.(in Chinese)
[12]Accellera.Universal verification methodology 1.1user’s guide[M].California:Cadence Design Systems Inc,Mentor Graphics Corp.,Synopsys Inc.,2011.
[13]Hu Xiang-dong,Yang Jian-xin,Zhu Ying.Shenwei-1600:A high-performance multi-core microprocessor[J].Scientia Sinica Informationis,2015,45(4):513-522.(in Chinese)
[14]Zhang Chen-xi,Wang Zhi-ying,Zhang Chun-yuan,et al.Computer architecture[M].3rd Edition.Beijing:High Education Press,2006.(in Chinese)
[15]David P,John H.Computer architecture:A quantitative approach[M].4th Edition.San Francisco:Morgan Kaufmann Publishers,2006.
[3]张珩,沈海华.龙芯2号微处理器的功能验证[J].计算机研究与发展,2006,43(6):974-979.
[5]朱英,陈诚,李彦哲,等.一款高性能多核处理器FPGA验证平台的创建[J].计算机研究与发展,2014,51(6):1295-1303.
[11]张欣,黄凯,孟建熠,等.一种面向微处理器验证的分层随机激励方法[J].计算机应用研究,2010,27(4):1284-1288.
[13]胡向东,杨剑新,朱英.高性能多核处理器申威1600[J].中国科学:信息科学,2015,45(4):513-522.
[14]张晨曦,王志英,张春元,等.计算机系统结构[M].第三版.北京:高等教育出版社,2006.