基于MOS技术的神经元电路研究进展
|
摘要
设计一种具有多种神经元响应模式、结构紧凑、低功耗的神经元电路,对大规模神经形态硬件的构建具有重要意义。分析了LIF、Izhikevich两种神经元模型的基本原理,重点介绍了数字和模拟两类神经元电路的设计方法、工作原理和优缺点。最后,讨论了神经元电路的设计趋势以及挑战。
It was important to construct a large scale neuromorphic hardware which was composed of neuron circuits that were designed with compact structure, low power consumption and behaviors of biological neuron. The basic principles of LIF and Izhikevich neuron models were first analyzed. Then, the design methods, mechanisms and characteristics of digital and analog neuron circuits were introduced. Finally, the design tendency and challenges of neuron circuits were discussed.
It was important to construct a large scale neuromorphic hardware which was composed of neuron circuits that were designed with compact structure, low power consumption and behaviors of biological neuron. The basic principles of LIF and Izhikevich neuron models were first analyzed. Then, the design methods, mechanisms and characteristics of digital and analog neuron circuits were introduced. Finally, the design tendency and challenges of neuron circuits were discussed.
引文
[1] MEAD C.Neuromorphic electronic systems [J].Proceed IEEE,1990,78(10):1629-1636.
[2] INDIVERI G,LIU S C.Memory and information processing in neuromorphic systems [J].Proceed IEEE,2015,103(8):1379-1397.
[3] JOUBERT A,BELHADJ B,TEMAM O,et al.Hardware spiking neurons design:analog or digital [C] // IEEE IJCNN.Brisbane,Australia.2012:11-15.
[4] IZHIKEVICH E M.Which model to use for cortical spiking neurons?[J].IEEE Trans Neur Network,2004,15(5):1063-1070.
[5] 徐泠风,李传东,陈玲.神经元模型对比分析 [J].物理学报,2016,65(24):1-12.
[6] IZHIKEVICH E M.Simple model of spiking neurons [J].IEEE Trans Neur Network,2003,14(6):1569-1572.
[7] MEAD C A.Analog VLSI and neural systems [M].Boston:Addison-Wesley Longman Publishing Co.,Inc.,1989.
[8] INDIVERI G,CHICCA E,DOUGLAS R.A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity [J].IEEE Trans Neur Network,2006,17(1):211-221.
[9] WIJEKOON J H,DUDEK P.Compact silicon neuron circuit with spiking and bursting behavior [J].Neur Network,2008,21(2):524-534.
[10] ZHANG J,WANG Y,ZHANG X,et al.Compact digital-controlled neuromorphic circuit with low power consumption [C] // IEEE ISCAS.Baltimore,MD,USA.2017:1-4.
[11] AKOPYAN F,SAWAD J,CASSIDY A,et al.TrueNorth:design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip [J].IEEE Trans Comput Aided Des Integr Circ & Syst,2015,34(10):1537-1557.
[12] CASSIDY A S,MEROLLA P,ARTHUR J V,et al.Cognitive computing building block:a versatile and efficient digital neuron model for neurosynaptic cores [C] // IEEE Int Joint Conf Neur Network.Dallas,TX,USA.2014:1-10.
[13] CASSIDY A,ANDREOU A G.Dynamical digital silicon neurons [C] // IEEE Biomed Circ & Syst Conf.Baltimore,MD,USA.2008:289-292.
[14] FRENKEL C,LEGAT J D,BOL D.A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors [C] // IEEE Biomed Circ & Syst Conf.Turin,Italy.2017:1-4.
[15] RANGAN V,GHOSH A,APARIN V,et al.A subthreshold aVLSI implementation of the Izhikevich simple neuron model [J].IEEE Engineer Medic Biol Soc,2009,17(11):4164-4167.
[16] IMAM N,WECKER K,TSE J,et al.Neural spiking dynamics in asynchronous digital circuits [C] // IEEE IJCNN.Dallas,TX,USA.2013:1-8.
[17] MEROLLA P,ARTHUR J,AKOPYAN F,et al.A digital neurosynaptic core using embedded crossbar memory with 45 pJ per spike in 45 nm [C] // IEEE Custom Integr Circ Conf.San Jose,CA,USA.2011:1-4.
[18] PARK J,HA S,YU T,et al.A 65 k-neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate - and - fire array transceiver [C] // IEEE Biomed Circ & Syst Conf.Lausanne,Switzerland.2014:675-678.
[19] SOURIKOPOULOS I,HEDAYAT S,LOYEZ C,et al.A 4-fJ/spike artificial neuron in 65 nm CMOS technology [J].Front Neurosci,2017,11(1):123.
[20] ZHANG L,ZHANG J,WANG Y,et al.A multi-mode silicon neuron circuit with high robustness against PVT variation [C] // IEEE Int Symp Circ & Syst.Florence,Italy.2018:1-4.
[2] INDIVERI G,LIU S C.Memory and information processing in neuromorphic systems [J].Proceed IEEE,2015,103(8):1379-1397.
[3] JOUBERT A,BELHADJ B,TEMAM O,et al.Hardware spiking neurons design:analog or digital [C] // IEEE IJCNN.Brisbane,Australia.2012:11-15.
[4] IZHIKEVICH E M.Which model to use for cortical spiking neurons?[J].IEEE Trans Neur Network,2004,15(5):1063-1070.
[5] 徐泠风,李传东,陈玲.神经元模型对比分析 [J].物理学报,2016,65(24):1-12.
[6] IZHIKEVICH E M.Simple model of spiking neurons [J].IEEE Trans Neur Network,2003,14(6):1569-1572.
[7] MEAD C A.Analog VLSI and neural systems [M].Boston:Addison-Wesley Longman Publishing Co.,Inc.,1989.
[8] INDIVERI G,CHICCA E,DOUGLAS R.A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity [J].IEEE Trans Neur Network,2006,17(1):211-221.
[9] WIJEKOON J H,DUDEK P.Compact silicon neuron circuit with spiking and bursting behavior [J].Neur Network,2008,21(2):524-534.
[10] ZHANG J,WANG Y,ZHANG X,et al.Compact digital-controlled neuromorphic circuit with low power consumption [C] // IEEE ISCAS.Baltimore,MD,USA.2017:1-4.
[11] AKOPYAN F,SAWAD J,CASSIDY A,et al.TrueNorth:design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip [J].IEEE Trans Comput Aided Des Integr Circ & Syst,2015,34(10):1537-1557.
[12] CASSIDY A S,MEROLLA P,ARTHUR J V,et al.Cognitive computing building block:a versatile and efficient digital neuron model for neurosynaptic cores [C] // IEEE Int Joint Conf Neur Network.Dallas,TX,USA.2014:1-10.
[13] CASSIDY A,ANDREOU A G.Dynamical digital silicon neurons [C] // IEEE Biomed Circ & Syst Conf.Baltimore,MD,USA.2008:289-292.
[14] FRENKEL C,LEGAT J D,BOL D.A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors [C] // IEEE Biomed Circ & Syst Conf.Turin,Italy.2017:1-4.
[15] RANGAN V,GHOSH A,APARIN V,et al.A subthreshold aVLSI implementation of the Izhikevich simple neuron model [J].IEEE Engineer Medic Biol Soc,2009,17(11):4164-4167.
[16] IMAM N,WECKER K,TSE J,et al.Neural spiking dynamics in asynchronous digital circuits [C] // IEEE IJCNN.Dallas,TX,USA.2013:1-8.
[17] MEROLLA P,ARTHUR J,AKOPYAN F,et al.A digital neurosynaptic core using embedded crossbar memory with 45 pJ per spike in 45 nm [C] // IEEE Custom Integr Circ Conf.San Jose,CA,USA.2011:1-4.
[18] PARK J,HA S,YU T,et al.A 65 k-neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate - and - fire array transceiver [C] // IEEE Biomed Circ & Syst Conf.Lausanne,Switzerland.2014:675-678.
[19] SOURIKOPOULOS I,HEDAYAT S,LOYEZ C,et al.A 4-fJ/spike artificial neuron in 65 nm CMOS technology [J].Front Neurosci,2017,11(1):123.
[20] ZHANG L,ZHANG J,WANG Y,et al.A multi-mode silicon neuron circuit with high robustness against PVT variation [C] // IEEE Int Symp Circ & Syst.Florence,Italy.2018:1-4.