用于无源RFID标签的拓展PSRR带宽无片外电容LDO
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摘要
经过调制的射频信号整流后会为无源射频识别(RFID)标签引入数万到几十万赫兹的电源纹波。为了抑制这种电源纹波,设计了一款1 MHz带宽内高电源电压抑制比(PSRR)、超低功耗、无片外电容低压差线性稳压器(LDO)。利用超级源跟随器结构改变传统LDO环路的极点分布,将输出极点作为环路主极点,将低频PSRR带宽有效拓展到1 MHz。利用动态偏置技术和双零点补偿结构保证环路稳定性。该LDO采用TSMC 0.18μm CMOS工艺实现,芯片面积约0.017 mm~2。测试结果表明:LDO在1 MHz频率范围内的PSRR小于-46 dB,轻负载下的PSRR可达-57 dB;电路消耗0.33~3.4μA的静态电流;在工作电压为1.1~3 V时输入电压调整率为4.6 mV/V;在负载电流为0~25μA时负载调整率为0.3 mV/μA;该LDO仅采用35 pF片上电容。
The modulated RF signal after being rectified will bring in power supply ripple with frequency range from tens to hundreds k Hz for passive radio frequency identification( RFID) tags. A 1 MHz bandwidth-extended power supply rejection ratio( PSRR),ultra-low power consumption,capacitorfree low drop-out regulator( LDO) was designed to suppress the power supply ripple. Super source follower structure was adopted to change the loop poles distribution in traditional LDO structure,which makes the output pole become the dominant pole and effectively expands the low frequency PSRR bandwidth to 1 MHz. The dynamic biase technology and double-zero compensation structure were used to ensure the stability of the loop. The proposed LDO with an area of about 0. 017 mm~2 was fabricated in TSMC0. 18 μm COMS process. The measured results show that the proposed LDO achieves a PSRR less than -46 dB at the frequency of 1 MHz and even -57 d B under light load condition. The quiescent current of the circuit is between 0. 33 and 3. 4 μA. Additionally,the line regulation is 4. 6 mV/V with a voltage supply range from 1. 1 V to 3 V,and the load regulation is 0. 3 mV/μA with the load current range from 0 μA to 25 μA. Moreover,the total on-chip capacitance of the LDO is as little as 35 p F.
The modulated RF signal after being rectified will bring in power supply ripple with frequency range from tens to hundreds k Hz for passive radio frequency identification( RFID) tags. A 1 MHz bandwidth-extended power supply rejection ratio( PSRR),ultra-low power consumption,capacitorfree low drop-out regulator( LDO) was designed to suppress the power supply ripple. Super source follower structure was adopted to change the loop poles distribution in traditional LDO structure,which makes the output pole become the dominant pole and effectively expands the low frequency PSRR bandwidth to 1 MHz. The dynamic biase technology and double-zero compensation structure were used to ensure the stability of the loop. The proposed LDO with an area of about 0. 017 mm~2 was fabricated in TSMC0. 18 μm COMS process. The measured results show that the proposed LDO achieves a PSRR less than -46 dB at the frequency of 1 MHz and even -57 d B under light load condition. The quiescent current of the circuit is between 0. 33 and 3. 4 μA. Additionally,the line regulation is 4. 6 mV/V with a voltage supply range from 1. 1 V to 3 V,and the load regulation is 0. 3 mV/μA with the load current range from 0 μA to 25 μA. Moreover,the total on-chip capacitance of the LDO is as little as 35 p F.
引文
[1]EL-NOZAHI M,AMER A,TORRES J,et al.High PSR low drop-out regulator with feed-forward ripple cancellation technique[J].IEEE Journal of Solid-State Circuits,2010,45(3):565-577.
[2]PARK C J,ONABAJO M,SILVA-MARTINEZ J.External capacitor-less low drop-out regulator with 25 d B supe-rior power supply rejection in the 0.4-4 MHz range[J].IEEE Journal of Solid-State Circuits,2014,49(2):486-501.
[3]CHEN L Y,CHENG Q,GUO J P,et al.High-PSR CMOS LDO with embedded ripple feedforward and energy-efficient bandwidth extension[C]∥Proceedings of IEEE International System-On-Chip Conference.Beijing,China,2015:384-389.
[4]ZARATE-ROLDAN J,WANG M D,TORRES J,et al.A capacitor-less LDO with high-frequency PSR suitable for a wide range of on-chip capacitive loads[J].IEEE Transactions on Very Large Scale Integration Systems,2016,24(9):2970-2982.
[5]YUN S J,KIM J S,YONG S K.Capless LDO regulator achieving-76 d B PSR and 96.3 fs FOM[J].IEEE Transactions on Circuits&Systems II:Express Briefs,2017,64(10):1147-1151.
[6]王忆.高性能低压差线性稳压器研究与设计[D].杭州:浙江大学,2010.
[7]HU J,HU B,FAN Y,et al.A 500 n A quiescent,100 m A maximum load CMOS low-dropout regulator[C]∥Proceedings of IEEE International Conference on Electronics,Circuits and Systems.Beirut,Lebanon,2011:386-389.
[8]DEGRAUWE M G,RIJMENANTS J,VITTOZ E A,et al.Adaptive biasing CMOS amplifiers[J].IEEE Journal of Solid-State Circuits,1982,17(3):522-528.
[9]WANG L,MAO W,WU C,et al.A fast transient LDO based on dual loop FVF with high PSRR[C]∥Proceedings of IEEE Asia Pacific Conference on Circuits and Systems.Jeju,South Korea,2016:99-102.
[10]GERVACIO J L G,MAY A L H,MEJIA G Z,et al.Voltage regulation system for UHF RFID tags[C]∥Symposium on Integrated Circuits and Systems Design.Curitiba,Brazil,2013:1-6.
[11]ZENG Y,TAN H Z.A FVF based LDO with dynamic bias current for low power RFID chips[C]∥Proceedings of IEEE International Conference on RFID Technology and Applications.Foshan,China,2016:61-64.
[2]PARK C J,ONABAJO M,SILVA-MARTINEZ J.External capacitor-less low drop-out regulator with 25 d B supe-rior power supply rejection in the 0.4-4 MHz range[J].IEEE Journal of Solid-State Circuits,2014,49(2):486-501.
[3]CHEN L Y,CHENG Q,GUO J P,et al.High-PSR CMOS LDO with embedded ripple feedforward and energy-efficient bandwidth extension[C]∥Proceedings of IEEE International System-On-Chip Conference.Beijing,China,2015:384-389.
[4]ZARATE-ROLDAN J,WANG M D,TORRES J,et al.A capacitor-less LDO with high-frequency PSR suitable for a wide range of on-chip capacitive loads[J].IEEE Transactions on Very Large Scale Integration Systems,2016,24(9):2970-2982.
[5]YUN S J,KIM J S,YONG S K.Capless LDO regulator achieving-76 d B PSR and 96.3 fs FOM[J].IEEE Transactions on Circuits&Systems II:Express Briefs,2017,64(10):1147-1151.
[6]王忆.高性能低压差线性稳压器研究与设计[D].杭州:浙江大学,2010.
[7]HU J,HU B,FAN Y,et al.A 500 n A quiescent,100 m A maximum load CMOS low-dropout regulator[C]∥Proceedings of IEEE International Conference on Electronics,Circuits and Systems.Beirut,Lebanon,2011:386-389.
[8]DEGRAUWE M G,RIJMENANTS J,VITTOZ E A,et al.Adaptive biasing CMOS amplifiers[J].IEEE Journal of Solid-State Circuits,1982,17(3):522-528.
[9]WANG L,MAO W,WU C,et al.A fast transient LDO based on dual loop FVF with high PSRR[C]∥Proceedings of IEEE Asia Pacific Conference on Circuits and Systems.Jeju,South Korea,2016:99-102.
[10]GERVACIO J L G,MAY A L H,MEJIA G Z,et al.Voltage regulation system for UHF RFID tags[C]∥Symposium on Integrated Circuits and Systems Design.Curitiba,Brazil,2013:1-6.
[11]ZENG Y,TAN H Z.A FVF based LDO with dynamic bias current for low power RFID chips[C]∥Proceedings of IEEE International Conference on RFID Technology and Applications.Foshan,China,2016:61-64.