基于CMOS工艺的并联双反馈跨阻放大器的设计与实现
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摘要
针对传统调节型共源共栅(RGC)跨阻放大器在带宽和增益方面的不足,提出1种可拓展带宽和优化平坦度的并联双反馈结构的全差分跨阻放大器.另外,采用反相器替代共源极辅助放大器来提高增益,减小等效输入噪声电流.输出缓冲级的输入端引入无源电感形成π型网络,以抵消其寄生电容.基于UMC 0.18μm CMOS工艺,制备出所设计的跨阻放大器芯片,并将其压焊在FR-4基材的印刷电路板上.测试结果表明,差分跨阻放大器的-3 d B带宽为3.5 GHz,总跨阻增益达60 d BΩ,工作频带内的群延时波动小于25 ps,平均等效输入噪声电流密度为18.72 pA/√Hz.在1.8 V工作电压下,芯片功耗为32.4 mW,裸片面积为800μm×600μm.
To optimize the bandwidth and gain performance of the traditional trans-impedance amplifier(TIA) with regulated cascode(RGC) topology, an enhanced differential amplifier with parallel shunt-feedback configuration is proposed to expand the bandwidth and optimize the flatness. Furthermore, the common source auxiliary amplifier in traditional RGC trans-impedance amplifier is instead of an inverter to increase the gain and reduce the overall circuit equivalent input noise current. Passive inductors applied to the input of output buffer stage formed π type network in order to compensate for parasitic capacitance of output buffer. Based on UMC0.18 μm CMOS process, a TIA with modified RGC configuration was optimized and implemented, and the fabricated chip was mounted on a FR-4 printed circuit board. The experimental results indicate that the fabricated TIA achieves a 3 d B bandwidth of 3.5 GHz with a differential gain of 60 d BΩ, and the fluctuation of group delay is less than 25 ps within the interesting band. Additionally, the average equivalent input noise current density measured by an oscilloscope is around 18.72 p A/Hz. The chip dissipates 32.4 mW at 1.8 V supply voltage, and the die area including pad is 800 μm×600 μm.
To optimize the bandwidth and gain performance of the traditional trans-impedance amplifier(TIA) with regulated cascode(RGC) topology, an enhanced differential amplifier with parallel shunt-feedback configuration is proposed to expand the bandwidth and optimize the flatness. Furthermore, the common source auxiliary amplifier in traditional RGC trans-impedance amplifier is instead of an inverter to increase the gain and reduce the overall circuit equivalent input noise current. Passive inductors applied to the input of output buffer stage formed π type network in order to compensate for parasitic capacitance of output buffer. Based on UMC0.18 μm CMOS process, a TIA with modified RGC configuration was optimized and implemented, and the fabricated chip was mounted on a FR-4 printed circuit board. The experimental results indicate that the fabricated TIA achieves a 3 d B bandwidth of 3.5 GHz with a differential gain of 60 d BΩ, and the fluctuation of group delay is less than 25 ps within the interesting band. Additionally, the average equivalent input noise current density measured by an oscilloscope is around 18.72 p A/Hz. The chip dissipates 32.4 mW at 1.8 V supply voltage, and the die area including pad is 800 μm×600 μm.
引文
1 Matera F.Dynamic optical networks for future internet environments[J].Fiber and Integrated Optics,2014,33(3):251-265.
2 Chen Sun,Mark T W,Yunsup L,et al.Single-chip microprocessor that communicates directly using light[J].Nature,2015,528(7 583):534-538.
3 Liu Lianxi,Zhao Jiao,En Yunfei,et al.A high gain wide dynamic range transimpedance amplifier for optical receivers[J].Journal of Semiconductors,2014,35(1):015001.
4 何林波,盛志伟,蔺冰.基于社会距离的下一代网络宽带资源分配的方法研究[J].南开大学学报:自然科学版,2015,48(4):5-11.
5 郭增笑,谢生,付友,等.基于标准Bi CMOS工艺的1.5 Gb/s调节型共源共栅光接收机[J].光电子·激光,2013,25(1):26-30.
6 Young H K,Sang S L.A 72 d BΩ11.43 m A novel CMOS regulated cascode TIA for 3.125 Gb/s optical communications[C/OL]//IEEE Circuits and Systems Society:26th IEEE International System-on-Chip Conference,September 4-6,2013,Erlangen,Germany.[2016-08-05].http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6749644.
7 Sushmit G,Jason S,Tino C,et al.A 14 m W 5 Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects[C/OL]//Institute of Electrical And Electronic Engineers:IEEE International Solid-State Circuits Conference,February 8-12,2009,San Francisco,America.[2016-08-06].http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4977284.
8 Chen Yingmei,Wang Zhigong,Fan Xiangning,et al.A 38 Gb/s to 43 Gb/s monolithic optical receiver in 65nm CMOS technology[J].IEEE Transactions on Circuits and Systems—I:Regular Papers,2013,60(12):3 173-3 181.
9 Young H K,Eui S J,Sang S L.Bandwidth enhancement technique for CMOS RGC transimpedance amplifier[J].Electronics Letters,2014,50(12):882-884.
10 Lu Zhenghao,Chen Dandan,Yeo K S.An inductor-less broadband design technique for transimpedance amplifiers[C/OL]//IEEE Solid-State Circuits Society Singapore Chapter:IEEE Proceedings of the 2009 12th International Symposium on Integrated Circuits,December 14-16,2009,Suntec,Singapore.[2016-08-06].Http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5403690.
11 Mohamed A,Horst Z.Low-power 10 Gb/s inductor-less inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS[J].Analog Integrated Circuits and Signal Processing,2013,76(3):367-376.
12 Amid S B,Plett C,Schvan P.Fully differential,40 Gb/s regulated cascode transimpedance amplifier in 0.13μm Si Ge Bi CMOS technology[C/OL]//IEEE BCTM Committee:IEEE Bipolar/BICMOS Circuits and Technology Meeting,October 4-6,2010,Austin,America.[2016-08-06].Http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5506763.
13 Eduard S.The transimpedance limit[J].IEEE Transactions on Circuits and Systems-I:Regular Papers,2010,57(8):1 848-1 856.
14 Behzad R.Design of analog CMOS integrated circuits[M].New York:Mc Graw-Hill Education,2000.
15 Behzad R.Design of integrated circuits for optical communications[M].New York:Mc Graw-Hill Education,2005.
16 Nga T H N,Ikechi A U,Jamshid S,et al.0.013 mm2and low-power 10 Gb/s transimpedance amplifier for short-reach optical interconnects[J].Microwave and Optical Technology Letters,2013,55(10):2 484-2 487.
2 Chen Sun,Mark T W,Yunsup L,et al.Single-chip microprocessor that communicates directly using light[J].Nature,2015,528(7 583):534-538.
3 Liu Lianxi,Zhao Jiao,En Yunfei,et al.A high gain wide dynamic range transimpedance amplifier for optical receivers[J].Journal of Semiconductors,2014,35(1):015001.
4 何林波,盛志伟,蔺冰.基于社会距离的下一代网络宽带资源分配的方法研究[J].南开大学学报:自然科学版,2015,48(4):5-11.
5 郭增笑,谢生,付友,等.基于标准Bi CMOS工艺的1.5 Gb/s调节型共源共栅光接收机[J].光电子·激光,2013,25(1):26-30.
6 Young H K,Sang S L.A 72 d BΩ11.43 m A novel CMOS regulated cascode TIA for 3.125 Gb/s optical communications[C/OL]//IEEE Circuits and Systems Society:26th IEEE International System-on-Chip Conference,September 4-6,2013,Erlangen,Germany.[2016-08-05].http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6749644.
7 Sushmit G,Jason S,Tino C,et al.A 14 m W 5 Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects[C/OL]//Institute of Electrical And Electronic Engineers:IEEE International Solid-State Circuits Conference,February 8-12,2009,San Francisco,America.[2016-08-06].http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4977284.
8 Chen Yingmei,Wang Zhigong,Fan Xiangning,et al.A 38 Gb/s to 43 Gb/s monolithic optical receiver in 65nm CMOS technology[J].IEEE Transactions on Circuits and Systems—I:Regular Papers,2013,60(12):3 173-3 181.
9 Young H K,Eui S J,Sang S L.Bandwidth enhancement technique for CMOS RGC transimpedance amplifier[J].Electronics Letters,2014,50(12):882-884.
10 Lu Zhenghao,Chen Dandan,Yeo K S.An inductor-less broadband design technique for transimpedance amplifiers[C/OL]//IEEE Solid-State Circuits Society Singapore Chapter:IEEE Proceedings of the 2009 12th International Symposium on Integrated Circuits,December 14-16,2009,Suntec,Singapore.[2016-08-06].Http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5403690.
11 Mohamed A,Horst Z.Low-power 10 Gb/s inductor-less inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS[J].Analog Integrated Circuits and Signal Processing,2013,76(3):367-376.
12 Amid S B,Plett C,Schvan P.Fully differential,40 Gb/s regulated cascode transimpedance amplifier in 0.13μm Si Ge Bi CMOS technology[C/OL]//IEEE BCTM Committee:IEEE Bipolar/BICMOS Circuits and Technology Meeting,October 4-6,2010,Austin,America.[2016-08-06].Http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5506763.
13 Eduard S.The transimpedance limit[J].IEEE Transactions on Circuits and Systems-I:Regular Papers,2010,57(8):1 848-1 856.
14 Behzad R.Design of analog CMOS integrated circuits[M].New York:Mc Graw-Hill Education,2000.
15 Behzad R.Design of integrated circuits for optical communications[M].New York:Mc Graw-Hill Education,2005.
16 Nga T H N,Ikechi A U,Jamshid S,et al.0.013 mm2and low-power 10 Gb/s transimpedance amplifier for short-reach optical interconnects[J].Microwave and Optical Technology Letters,2013,55(10):2 484-2 487.