3D堆叠封装硅通孔结构的电-热-结构耦合分析
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摘要
硅通孔(TSV)技术作为三维封装的关键技术,其可靠性问题受到广泛的关注。基于ANSYS平台,通过有限元方法,对3D堆叠封装的TSV模型进行了电-热-结构耦合分析,并进一步研究了不同的通孔直径、通孔高度以及介质隔离层SiO_2厚度对TSV通孔的电流密度、温度场及热应力分布的影响。结果表明:在TSV/微凸点界面的拐角处存在较大的电流密度和等效应力,容易引起TSV结构的失效;增大通孔直径、减小通孔长度可以提高TSV结构的电-热-机械可靠性;随着SiO_2层厚度的增加,通孔的最大电流密度增大而最大等效应力减小,需要综合考虑合理选择SiO_2层厚度。
As the key technology of three-dimensional packaging,the reliability of the through silicon via(TSV) technology has attracted wide attention.Based on ANSYS platform,the electric-thermo-structural coupling analysis of the TSV model of 3 D stacked packaging was carried out by finite element method.The effects of different TSV diameter,TSV height and the thickness of SiO_2 on the current density,the temperature and thermal stress distribution of the TSV were then studied.The results show that large current density and von-Mises stress exist at the corner of the TSV/micro bump interface,which may lead to the failure of TSV structure.Larger diameter and shorter length can improve the electric-thermo-structural reliability of TSV structures.As SiO_2 layer thickness increases,the maximum current density increases,while the maximum von-Mises stress decreases.As a result,it is necessary to choose the thickness of SiO_2 layer carefully.
As the key technology of three-dimensional packaging,the reliability of the through silicon via(TSV) technology has attracted wide attention.Based on ANSYS platform,the electric-thermo-structural coupling analysis of the TSV model of 3 D stacked packaging was carried out by finite element method.The effects of different TSV diameter,TSV height and the thickness of SiO_2 on the current density,the temperature and thermal stress distribution of the TSV were then studied.The results show that large current density and von-Mises stress exist at the corner of the TSV/micro bump interface,which may lead to the failure of TSV structure.Larger diameter and shorter length can improve the electric-thermo-structural reliability of TSV structures.As SiO_2 layer thickness increases,the maximum current density increases,while the maximum von-Mises stress decreases.As a result,it is necessary to choose the thickness of SiO_2 layer carefully.
引文
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[2]董刚,姚奕彤,刘荡,等.硅通孔热应力导致器件迁移率变化分析 [J].西安电子科技大学学报,2017,44(6):83-87.
[3]Kinoshita T,Kawakami T,Hori T,et al.Thermal stresses of through silicon vias and Si chips in three dimensional system in package [J].Journal of Electronic Packaging,2012,134(2):20903.
[4]薛彤,张国华,杨轶博.多种结构硅通孔热应力仿真分析 [J].微电子学,2015,45(6):820-824.
[5]黄春跃,梁颖,熊国际,等.基于热-结构耦合的3D-TSV互连结构的应力应变分析 [J].电子元件与材料,2014,33(7):85-90.
[6]袁琰红,高立明,吴昊,等.硅通孔尺寸与材料对热应力的影响 [J].半导体光电,2013,34(2):255-258.
[7]赵健,崔玉强,焦科名.基于复合介质层材料的硅通孔热结构耦合分析 [J].微电子学,2017,47(6):837-841.
[8]Song M,Mundboth K R,Szpunar J A,et al.Characterization of local strain/stress in copper through-silicon via structures using synchrotron X-ray microdiffraction,electron backscattered diffraction and nonlinear thermomechanical model [J].Journal of Micromechanics and Microengineering,2015,25(8):0850028.
[9]Kosemura D,De Wolf I.Three-dimensional micro-Raman spectroscopy mapping of stress induced in Si by Cu-filled through-Si vias [J].Applied Physics Letters,2015,106:19190119.
[10]Bahareh B,Suresh R,Liu H L,et al.Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps [C]//2012 IEEE 62nd Electronic Components and Technology Conference.NY,USA:IEEE,2012.
[11]孙汉,王玮,陈兢,等.硅通孔(TSV)的工艺引入热应力及其释放结构设计 [J].应用数学和力学,2014,35(3):295-304.