基于积分结构的数字正切锁相环改进设计
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摘要
针对时延数字正切锁相环存在跟踪盲区、环路建立时间长和非线性等问题,提出一种基于积分结构的改进数字正切锁相环设计。为使鉴相器具有更好的线性特征,采用积分结构代替固定时延单元。通过提取信号幅度中的频率信息并将其用于频率粗调,可较大幅度的减少频率跟踪时间。对积分结构的数字正切锁相环进行了理论描述和分析,并利用System Generator建立设计模型并仿真。结果表明,积分结构的数字正切锁相环不仅能够消除跟踪盲区,提高相位鉴别精度,还能较快进入锁定状态,减少约31%的锁定时间,改进效果明显。
Digital delay locked loop for tangent(TDTL) has some shortcomings such as the presence of blind tracking, long time to establish and nonlinear etc. Presenting a new integral-based tan lock loop(IDTL). It used an integral structure instead of a fixed-time delay unit to strictly maintain the orthogonal relationship between the two loops, and can get a good linear phase detector, and extract the phase-shifted signal amplitude frequency information for frequency coarse tunning, which significantly reduces the frequency tracking time. There is also discussed the basical pricinple of the design and implemented its model for simulation. The conclusion shows that the design can eliminate the presence of blind tracking, and has a good linear phase detector, and can lock in a faster way with reducing 31 percent of the time.
Digital delay locked loop for tangent(TDTL) has some shortcomings such as the presence of blind tracking, long time to establish and nonlinear etc. Presenting a new integral-based tan lock loop(IDTL). It used an integral structure instead of a fixed-time delay unit to strictly maintain the orthogonal relationship between the two loops, and can get a good linear phase detector, and extract the phase-shifted signal amplitude frequency information for frequency coarse tunning, which significantly reduces the frequency tracking time. There is also discussed the basical pricinple of the design and implemented its model for simulation. The conclusion shows that the design can eliminate the presence of blind tracking, and has a good linear phase detector, and can lock in a faster way with reducing 31 percent of the time.
引文
[1]孙高阳,刘亚静,李秉格,等. 一种消除反馈延迟的全数字锁相环[J]. 电工技术学报, 2017, 32(20):171-178.
[2]AL-QUTAYRI M A, AL-ARAJI S R, AL-ALI O A, et al. Time delay digital tanlock loop with linearized phase detector[C]. IEEE International Conference on Electronics, Circuits, and Systems. IEEE, 2009:555-558.
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[5]何文青,宋春林,董航,等. 数字锁相环提取位同步信号的改进与实现[J]. 无线电通信技术, 2015, 41(1):74-76.
[6]AL-ALI A K, AL-ARAJI S, ANANI N, et al. Adaptive TDTL using frequency and phase processing techniques[C]. International Conference on Information Sciences Signal Processing and Their Applications. IEEE, 2010:530-533.
[7]纪志成,高春能,吴定会. FPGA数字信号处理设计教程:System generator入门与提高[M]. 西安:西安电子科技大学出版社, 2008: 188-189.
[8]姚亚峰,孙金傲,霍兴华,等. 一种结合高精度TDC的快速全数字锁相环[J]. 湖南大学学报(自然科学版), 2017, 44(8):131-136.
[9]龚锦霞,解大,张延迟. 三相数字锁相环的原理及性能[J]. 电工技术学报, 2009, 24(10):94-99.
[10]谭聪,卜海祥,唐璞山. 一种改进的用于FPGA的快速数字锁相环电路设计[J]. 复旦学报(自然科学版), 2009, 48(4):470-476.
[2]AL-QUTAYRI M A, AL-ARAJI S R, AL-ALI O A, et al. Time delay digital tanlock loop with linearized phase detector[C]. IEEE International Conference on Electronics, Circuits, and Systems. IEEE, 2009:555-558.
[3]李凤华,刘丹丹,单长虹. 一种可编程全数字锁相环的设计与实现[J]. 计算机测量与控制, 2016, 24(1):243-245.
[4]陆原,汪周玮,郭素兵. 基于单二阶广义积分器的三相数字锁相环设计[J]. 电测与仪表,2015, 52(6):96-101.
[5]何文青,宋春林,董航,等. 数字锁相环提取位同步信号的改进与实现[J]. 无线电通信技术, 2015, 41(1):74-76.
[6]AL-ALI A K, AL-ARAJI S, ANANI N, et al. Adaptive TDTL using frequency and phase processing techniques[C]. International Conference on Information Sciences Signal Processing and Their Applications. IEEE, 2010:530-533.
[7]纪志成,高春能,吴定会. FPGA数字信号处理设计教程:System generator入门与提高[M]. 西安:西安电子科技大学出版社, 2008: 188-189.
[8]姚亚峰,孙金傲,霍兴华,等. 一种结合高精度TDC的快速全数字锁相环[J]. 湖南大学学报(自然科学版), 2017, 44(8):131-136.
[9]龚锦霞,解大,张延迟. 三相数字锁相环的原理及性能[J]. 电工技术学报, 2009, 24(10):94-99.
[10]谭聪,卜海祥,唐璞山. 一种改进的用于FPGA的快速数字锁相环电路设计[J]. 复旦学报(自然科学版), 2009, 48(4):470-476.