基于Qsys的FFT组件IP核设计及应用
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摘要
使用FPGA开发工具Qsys自定制组件的方法,设计了一种具有Avalon总线接口的快速傅立叶变换IP核,能够方便地挂接到NiosII软核处理器上,从而协助CPU实现快速傅里叶变换的功能.该IP核能够灵活的配置成8位、10位、12位或14位等位宽,也可以配置成能对2~n(n=6,7,8,…)个采样点进行傅立叶正变换或反变换.同时本文还给出了该IP核的一个应用范例,即在FPGA开发板上构建了一款音频信号分析仪的SOPC系统.实验结果表明,该IP核能够圆满的完成频谱分析和失真度分析的任务.该IP核具有使用方便、配置灵活、精度高等优点.
A Fast Fourier Transform IP core which can be added to Avalon bus is designed in this paper.The method of creating new component in Altera Company's Qsys tool is used in the design.The IP core can be parameterized as 8,10 or 12 bits width and so on,and the sampled data number can be parameterized as 2 to the nth power,here n is an integer from 6 to more.The IP core can also be configured as inverse transform and the input data can be complex numbers.This paper takes the audio frequency analyzer system as an application example whose SOPC system includes the FFT core on the DE2 developing board.The experimental result proves that the FFT IP core works perfectly,and has the advantages of feasible configuration,easy operation,and high precision.
A Fast Fourier Transform IP core which can be added to Avalon bus is designed in this paper.The method of creating new component in Altera Company's Qsys tool is used in the design.The IP core can be parameterized as 8,10 or 12 bits width and so on,and the sampled data number can be parameterized as 2 to the nth power,here n is an integer from 6 to more.The IP core can also be configured as inverse transform and the input data can be complex numbers.This paper takes the audio frequency analyzer system as an application example whose SOPC system includes the FFT core on the DE2 developing board.The experimental result proves that the FFT IP core works perfectly,and has the advantages of feasible configuration,easy operation,and high precision.
引文
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[2] 才华,陈广秋,刘广文,等.基于FPGA架构的可变点FFT处理器设计与实现[J].吉林大学学报(理学版),2018,56(1):151-158.
[3] 刘旭东,赵迎春,张艳芬.基于FFT加窗插值算法的应用研究[J].辽宁师专学报(自然科学版),2017,19(1):78-80.
[4] 雷元武,陈小文,彭元喜.DSP芯片中的高能效FFT加速器[J].计算机研究与发展,2016,53(7):1438-1446.
[5] 李艳凤,陈后金,胡健.浅析FFT算法中对称关系[J].电气电子教学学报,2017,39(5):78-84.
[6] 夏凯锋,周小平,吴斌.任意点存储器结构FFT处理器地址策略[J].北京理工大学学报,2017,37(9):953-957.
[7] 邹游.快速傅里叶变换裁剪算法[D].广州:华南理工大学,2017.
[8] 李宁,左培丽,王新刚,等.基于改进DFT和时域准同步的间谐波检测算法[J].电力自动化设备,2017,37(4):170-178.
[9] 付豪,周彬彬,喻伟闯,等.基于FPGA的4路信号发生器的设计[J].湖北民族学院学报(自然科学版),2016,34(2):203-206.
[10] 朱荣军.嵌入式车载导航双定位系统瞬时故障恢复方法[J].内蒙古民族大学学报(自然科学版),2018(6):485-488.
[11] 邵彩幸,于越,段琼,等.基于嵌入式与OpenCV的目标识别系统研究[J].西南民族大学学报(自然科学版),2018,44(5):66-70.
[12] 陈涛,杜传红,刘立才.GPS通信系统的设计[J].安顺学院学报,2018,20(5):132-135.
[13] WEI T,ZHANG J.The design of configurable display controller IP core based on SOPC system[C]// Seventh International Conference on Image & Graphics,2013.
[14] LIU S J,ZHOU H H,LI C.Design of remote engine room monitoring system based on niche stack TCP/IP[C]//The International Conference on Human-centric Computing 2011 and Embedded and Multimedia Computing,2011,102:417-425.
[15] 刘三军,向丽萍,徐建,等.基于多CPU的智能机房物联网系统[J].微电子学与计算机,2011,28(9):183-185.
[16] 王勇,张锦荣,林林,等.基于NiosII软核的嵌入式网络通信电路设计[J].科技视界,2015(30):28.
[17] 马昕煜,徐瀚洋,王健.SOC嵌入式数字IP核通用测试方法[J].微电子学与计算机,2019,36(2):26-30.
[18] 罗斌.IP核测试验证技术研究与应用[J].集成电路应用,2018,35(12):19-23.
[19] Altera Corporation.FFT MegaCore function user guide.Version 2.1.0[EB/OL].(2017-10-02)[2019-04-03]http://www.intel.cn/content/www/cn/zh/programmable/products/intellectual-property/ip/dsp/m-ham-fft.html.
[20] 李洪宾.新型12位高速、微功耗A/D转换器ADS7822及其应用[J].国外电子元器件,1998(8):20-21.
[21] 王成,范书义,余磊.基于NextKit的奈奎斯特采样定律示教系统[J].教育现代化,2016,3(24):164-173.