针对DDR3应用的800MHz低抖动扩频时钟发生器
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摘要
本文提出一种可编程扩频时钟发生器采用小数分频锁相环,扩频是以三角波通过ΣΔ调制器调制反馈分频器的方式实现。为了提高宽扩展比,采用一种技术保持三角波在ΣΔ调制器的输入范围内。使用的相位旋转技术由虚拟多相产生方法和相位补偿方法组成。该技术能有效地补偿瞬时时序误差和量化误差。可编程的时钟频率200-800 MHz伴随中心和向下扩展(0~10%),RMS周期抖动在输出时钟在800 MHz是7 ps。测试芯片在40纳米CMOS制造技术提供了输出时钟800 MHz时有10%扩张率,在10%扩频比时峰值减少是30分贝。所提出的可编程扩频时钟发生器从1.1 V电源消耗5.181m W,设计仅占0.105 mm~2的面积。
A programmable spread spectrum clock generator(SSCG)using fractional-N phase-locked loop(PLL)is presented. Spreading is achieved by modulating the feedback divider using a triangular wave through a ΣΔ modulator. In order to allow wide spreading ratios a technique is adopted to keep the triangular wave within the input range of the ΣΔ modulator. The used phase-rotating technique consists of virtual multiphase generation and the phase compensation approach. This technique can effectively compensates the instantaneous timing error. The clock frequency is programmable from 200-800 MHz with center and down spreading(0~10%). The RMS period jitter at output clock is 7 ps at 800 MHz. The test-chip fabricated in 40 nm CMOS technology provides 800 MHz output clock with 10 % spreading ratio. Peak reduction is 30 d B at 10 % spreading ratio. The proposed SSCG consumes 5.181 m W from 1.1 V supply and only occupies 0.105 mm2.
A programmable spread spectrum clock generator(SSCG)using fractional-N phase-locked loop(PLL)is presented. Spreading is achieved by modulating the feedback divider using a triangular wave through a ΣΔ modulator. In order to allow wide spreading ratios a technique is adopted to keep the triangular wave within the input range of the ΣΔ modulator. The used phase-rotating technique consists of virtual multiphase generation and the phase compensation approach. This technique can effectively compensates the instantaneous timing error. The clock frequency is programmable from 200-800 MHz with center and down spreading(0~10%). The RMS period jitter at output clock is 7 ps at 800 MHz. The test-chip fabricated in 40 nm CMOS technology provides 800 MHz output clock with 10 % spreading ratio. Peak reduction is 30 d B at 10 % spreading ratio. The proposed SSCG consumes 5.181 m W from 1.1 V supply and only occupies 0.105 mm2.
引文
[1]K.Shu,E.Sanchez-Sinencio,"CMOS PLL Synthesizers:Analysis and Design",Springer,2006.
[2]B.Razavi,"Design of Analog CMOS Integrated Circuits",New York:Mc Graw-Hill,2001,pp.377-400.
[3]I.A.Young,J.K.Greason and K.L.Wong,“A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”IEEE Journal of Solid-State Circuits,vol.27,pp.1599-1607,Nov.1992.
[4]K.B.Hardin,J.T.Fessler,and D.R.Bush,“Spread-spectrum clock generation for the reduction of radiated emissions,”in Proc.IEEE Int.Symp.Electromagn.Compat.,1994,pp.227-231.
[5]H.H.Chang,I.H.Hua,and S.I.Liu,"Aspread-spectrum clock generator with triangular modulation",IEEE Journal of Solid-state Circuits,vol.38,no.4,pp.673-676,April 2003.
[6]Y.B.Hsieh and Y.H.Kao,“A fully integrated spread-spectrum clock generator by using direct VCOmodulation,”IEEE Trans.Circuits Syst.I,Reg.Papers,vol.55,no.7,pp.1845-1853,Aug.2008.
[7]M.Kokubo,et al,"Spread-spectrum clock generator for serial ATA using fractional PLL controlled byΔΣmodulator with level shifter"IEEE Int.Solid-State Circuits Conf.Dig.Tech.Papers,pp.160-161,Feb.,2005.
[8]K.-H.Cheng,C.-L.Hung,and C.-H.Chang,“A0.77 ps RMS jitter 6-GHz spread-spectrum clock generator using a compensated phaserotating technique,”IEEE J.Solid-State Circuits,vol.46,no.5,pp.1198-1213,May 2011.
[9]C.S.Vaucher,"Architectures for RF Frequency Synthesizers",Kluwer academic publishers,2002.
[10]M.Kozak and I.Kale,"Oversampled Delta Sigma modulators",Kluwer academic publishers,2003,pp.25-30.
[11]M.Aoyama,K.Ogasawara,M.Sugawara,T.Ishibashi,T.Ishibashi,S.Shimoyama,K.Yamaguchi,T.Yanagita,and T.Noma,“3 Gbps,5000 ppm spread spectrum serdes PHY with frequency tracking phase interpolators for serial ATA,”in Symp.VLSI Circuits Dig.,Jun.2003,pp.107-110.
[12]J.Shin,I.Seo,J.Y.Kim,S.-H.Yang,C.Kim,J.Pak,H.Kim,M.Kwak,and G.Hong,“A low-jitter added SSCG with seamless phase selection and fast AFCfor 3rd generation serial-ATA,”in Proc.IEEE Custom Integrated Circuits Conf.,Sep.2006,pp.409-412.
[13]M.Zanuso,S.Levantino,C.Samori,and A.Lacaita,“A 3 MHz-BW 3.6 GHz digital fractional-N PLL with sub-gate-delay TDC,phase-interpolation divider,and digital mismatch cancellation,”in IEEE Int.Solid-State Circuit Conf.Dig.Tech.Papers,Feb.2010,pp.476-477.
[2]B.Razavi,"Design of Analog CMOS Integrated Circuits",New York:Mc Graw-Hill,2001,pp.377-400.
[3]I.A.Young,J.K.Greason and K.L.Wong,“A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”IEEE Journal of Solid-State Circuits,vol.27,pp.1599-1607,Nov.1992.
[4]K.B.Hardin,J.T.Fessler,and D.R.Bush,“Spread-spectrum clock generation for the reduction of radiated emissions,”in Proc.IEEE Int.Symp.Electromagn.Compat.,1994,pp.227-231.
[5]H.H.Chang,I.H.Hua,and S.I.Liu,"Aspread-spectrum clock generator with triangular modulation",IEEE Journal of Solid-state Circuits,vol.38,no.4,pp.673-676,April 2003.
[6]Y.B.Hsieh and Y.H.Kao,“A fully integrated spread-spectrum clock generator by using direct VCOmodulation,”IEEE Trans.Circuits Syst.I,Reg.Papers,vol.55,no.7,pp.1845-1853,Aug.2008.
[7]M.Kokubo,et al,"Spread-spectrum clock generator for serial ATA using fractional PLL controlled byΔΣmodulator with level shifter"IEEE Int.Solid-State Circuits Conf.Dig.Tech.Papers,pp.160-161,Feb.,2005.
[8]K.-H.Cheng,C.-L.Hung,and C.-H.Chang,“A0.77 ps RMS jitter 6-GHz spread-spectrum clock generator using a compensated phaserotating technique,”IEEE J.Solid-State Circuits,vol.46,no.5,pp.1198-1213,May 2011.
[9]C.S.Vaucher,"Architectures for RF Frequency Synthesizers",Kluwer academic publishers,2002.
[10]M.Kozak and I.Kale,"Oversampled Delta Sigma modulators",Kluwer academic publishers,2003,pp.25-30.
[11]M.Aoyama,K.Ogasawara,M.Sugawara,T.Ishibashi,T.Ishibashi,S.Shimoyama,K.Yamaguchi,T.Yanagita,and T.Noma,“3 Gbps,5000 ppm spread spectrum serdes PHY with frequency tracking phase interpolators for serial ATA,”in Symp.VLSI Circuits Dig.,Jun.2003,pp.107-110.
[12]J.Shin,I.Seo,J.Y.Kim,S.-H.Yang,C.Kim,J.Pak,H.Kim,M.Kwak,and G.Hong,“A low-jitter added SSCG with seamless phase selection and fast AFCfor 3rd generation serial-ATA,”in Proc.IEEE Custom Integrated Circuits Conf.,Sep.2006,pp.409-412.
[13]M.Zanuso,S.Levantino,C.Samori,and A.Lacaita,“A 3 MHz-BW 3.6 GHz digital fractional-N PLL with sub-gate-delay TDC,phase-interpolation divider,and digital mismatch cancellation,”in IEEE Int.Solid-State Circuit Conf.Dig.Tech.Papers,Feb.2010,pp.476-477.