一种带失调校准的高速高精度采样保持电路
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摘要
设计了一款基于0. 18μm CMOS工艺带失调校准的高速高精度两级采样保持电路。该电路选择开环双通道时间交织的采样保持架构,提高了整体采样保持电路的速率。通过采用高精度失调校准电路、改进的级间缓冲器以及栅压自举开关等来提高采样保持电路的精度。电路仿真结果表明,在电源电压为2 V,采样时钟为1. 6 GHz,输入信号频率为382. 8 MHz,第一级和第二级保持电容分别为0. 9 f F和0. 6 f F时,该电路的无杂散动态范围(SFDR)为85. 8 d B,总谐波失真(THD)为-81. 7 dB,有效位数(ENOB)为12. 6 Bits。
A high speed and high precision two stage sample and hold circuit based on 0. 18 μm CMOS process with offset calibration was designed. The circuit used an open loop two-channel time-interleaved architecture,which improved the speed of the overall sample and hold circuit. The accuracy of sample and hold circuit was improved by adopting high-precision offset calibration circuit,modified interstage buffer and bootstrapped switch. Simulation results show that the supply voltage is 2 V. The sampling clock is 1. 6 GHz and the input signal frequency is 382. 8 MHz. When the first and second holding capacitance is 0. 9 f F and 0. 6 f F respectively,the circuit's SFDR is 85. 8 d B,THD is-81. 7 d B,ENOB is 12. 6 Bits.
A high speed and high precision two stage sample and hold circuit based on 0. 18 μm CMOS process with offset calibration was designed. The circuit used an open loop two-channel time-interleaved architecture,which improved the speed of the overall sample and hold circuit. The accuracy of sample and hold circuit was improved by adopting high-precision offset calibration circuit,modified interstage buffer and bootstrapped switch. Simulation results show that the supply voltage is 2 V. The sampling clock is 1. 6 GHz and the input signal frequency is 382. 8 MHz. When the first and second holding capacitance is 0. 9 f F and 0. 6 f F respectively,the circuit's SFDR is 85. 8 d B,THD is-81. 7 d B,ENOB is 12. 6 Bits.
引文
[1] BUCK M. A 6-GS/s 9. 5-b Single-core pipelined foldingInterpolating ADC with 7. 3 ENOB and 52. 7-d Bc SFDR in the second nyquist band in 0. 25-μm Si Ge-BiCMOS[J].IEEE Transactions on Microwave Theory and Techniques.2017,65(2):414-422.
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[4]刘明,徐世六,张正平,等.一种基于CMOS工艺的高速采样保持电路的设计[J].微电子学,2014(3):285-288.
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[7]刘飞,贾嵩,卢振庭,等.带主从式T/H电路的折叠插值A/D转换器[J].半导体学报,2004(4):462-467.
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[9] POUYA P,GHASEMI A,AMINZADEH H. A low-voltage high-speed high-linearity MOSFET-only analog bootstrapped switch for sample-and-hold circuits[C]. Tehran:2nd International Conference on Knowledge-Based Engineering and Innovation(KBEI),2015:418-421.
[10]拉扎维·毕查德.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2003:341-344.
[2] FAN R,ZHOU K,MA Z,et al. A digital calibration design for10-bit folding and interpolating ADC[C]. IEEE International Conference of Electron Devices and Solid-State Circuits(EDSSC),2009:346-349.
[3]姚若河,朱建培,吴为敬,等. Flip-around结构高速采样保持电路的设计[J].微电子学,2006,36(2):225-228.
[4]刘明,徐世六,张正平,等.一种基于CMOS工艺的高速采样保持电路的设计[J].微电子学,2014(3):285-288.
[5] ABOLHASANI A,HADIDI K,TOHIDI M,et al. A new highresolution and high-speed open-loop CMOS sample and hold circuit[C]. Mashhad:21st Iranian Conference on Electrical Engineering(ICEE),2013:1-6.
[6]陈振中,王永禄,胡蓉彬,等.一种CMOS超高速主从式采样/保持电路[J].微电子学,2017(2):195-198.
[7]刘飞,贾嵩,卢振庭,等.带主从式T/H电路的折叠插值A/D转换器[J].半导体学报,2004(4):462-467.
[8]杨扬,王军,邓茗诚.一种高线性度CMOS栅压自举采样开关[J].通信技术,2012(11):99-101.
[9] POUYA P,GHASEMI A,AMINZADEH H. A low-voltage high-speed high-linearity MOSFET-only analog bootstrapped switch for sample-and-hold circuits[C]. Tehran:2nd International Conference on Knowledge-Based Engineering and Innovation(KBEI),2015:418-421.
[10]拉扎维·毕查德.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2003:341-344.