龙芯X微处理器抗辐照加固设计
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摘要
龙芯X微处理器芯片是一款集成了中央处理器、存储控制器、PCI控制器、周边元件扩展接口、通用输入/输出控制器、中断控制器、串行外围设备控制器、串行通讯总线控制器等丰富功能的SOC芯片.芯片采用32位MIPS龙芯自主知识产权处理器核LS232,并从多个层面对芯片进行抗辐照加固,包括环栅版图加固、guard-ring版图加固、时空三模冗余加固、DICE结构存储、EDAC算法加固等,使芯片能够适应各种复杂空间环境的应用需求.龙芯X芯片工作频率为100 MHz,总剂量抗辐照指标300 krad(Si)以上,单粒子GEO轨道翻转率小于1.90362×10-5/设备/天.
Loongson X-CPU is a highly integrated, high-performance 32-bit MIPS SOC based on the Loongson LS232 architecture. The chip operates at 100 MHz and contains a CPU, an EMI, separate instruction sets and data caches, an interrupt controller, a general-purpose I/O interface, two UARTs, a PCI interface, and a flexible memory controller. Through radiation hardening by design(RDHB) for multiple aspects, including circular-shape gate layout, guard-ring protect, time and space triple modular redundancy, dual interlocked storage cell, and error detection and correction coding, the chip can adapt to complex space environments and complicated application requirements. The chip was tested for up to a total dose of 300 krad(Si) and it yielded an SEU error rate better than 1.90362 × 10-5/device/day.
Loongson X-CPU is a highly integrated, high-performance 32-bit MIPS SOC based on the Loongson LS232 architecture. The chip operates at 100 MHz and contains a CPU, an EMI, separate instruction sets and data caches, an interrupt controller, a general-purpose I/O interface, two UARTs, a PCI interface, and a flexible memory controller. Through radiation hardening by design(RDHB) for multiple aspects, including circular-shape gate layout, guard-ring protect, time and space triple modular redundancy, dual interlocked storage cell, and error detection and correction coding, the chip can adapt to complex space environments and complicated application requirements. The chip was tested for up to a total dose of 300 krad(Si) and it yielded an SEU error rate better than 1.90362 × 10-5/device/day.
引文
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3 Velazco R,Fouillat P,Reis R.Radiation Effects on Embedded Systems.Netherlands:Springer,2007
4 Mayer D C,Lacoe R C,King E E,et al.Reliability enhancement in high-performance MOSFETs by annular transistor design.IEEE Trans Nucl Sci,2004,51:3615–3620
5 Anelli G,Campbell M,Delmastro M,et al.Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments:practical design aspects.IEEE Trans Nucl Sci,1999,46:1690–1696
6 Hatano H,Takatsuka S.Total dose radiation-hardened latch-up free CMOS structures for radiation-tolerant VLSI designs.IEEE Trans Nucl Sci,1986,33:1505–1509
7 Mitra S,Seifert N,Zhang M,et al.Robust system design with built-in soft-error resilience.Computer,2005,38:43–52
8 Faccio F.Single event effects in static and dynamic registers in a 0.25mm CMOS technology.IEEE Trans Nucl Sci,1999,46:1434–1439
9 Niranjan S,Frenzel J F.A comparison of fault-tolerant state machine architectures for space-borne electronics.IEEE Trans Nucl Sci,1996,45:109–113
10 Calin T,Nicolaidis M,Velazco R.Upset hardened memory design for submicron CMOS technology.IEEE Trans Nucl Sci,1996,43:2874–2878
11 Zhou Q,Mohanram K.Transistor sizing for radiation hardening.In:Proceedings of IEEE International Reliability Physics Symposium.Piscataway:IEEE,2004.310–315
12 Han Z S,Zhao Y F.Introduction to Radiation Hardened Integrated Circuit.Beijing:Tsinghua University Press,2011[韩郑生,赵元富.抗辐射集成电路概论.北京:清华大学出版社,2011]
13 Petersen E L.Single-event data analysis.IEEE Trans Nucl Sci,2008,55:2819–2841
14 Adatia A,Chan L K.Robust estimators of the 3-parameter weibull distribution.IEEE Trans Reliab,1985,R-34:347 –351
15 Mavis D G,Eaton P H.SEU and SET modeling and mitigation in deep submicron technologies.In:Proceedings of IEEE International Reliability Physics Symposium.Piscataway:IEEE,2007.293–305
1)JHU/APL Webmaster,http://vanallenprobes.jhuapl.edu/science/overview.php.
2)Commission of Science,Technology and Industry for National Defense(COSTIND),Standard Guide for Heavy Ion Single Event Effects Test of Aerospace Semiconductor Device,国防科学技术工业委员会.宇航用半导体器件重离子单粒子效应试验指南(QJ 10005-2008),2008.
3)Commission of Science,Technology and Industry for National Defense(COSTIND),Standard Guide for Total Dose Irradiation test of Aerospace semiconductor device,国防科学技术工业委员会.宇航用半导体器件总剂量辐照试验方法(QJ 10004-2008),2008.