片间高速图像传输系统的设计与实现
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摘要
针对图像采集与处理系统研发中的现场可编程门阵列(FPGA)之间的高速图像数据传输问题,设计了一种全双工、高吞吐率、高稳定性和高抗干扰能力的高速图像数据传输方案。设计的片间高速图像传输系统提供了通用的图像传输接口,可兼容不同的数据位宽和用户时钟频率。高速图像传输模块分为协议层和物理层。协议层包括跨时钟域电路和CXP图像传输协议编译码电路,完成跨时钟域和图像数据流编译码处理;物理层基于Aurora 8B/10B core,完成数据流的串并转换以及多通道绑定等处理,并采用GTH收发器实现高速串行数据的收发。仿真测试表明,图像数据传输正确,图像数据流同步时钟最高可达250 MHz,传输位宽达128 bit,最高吞吐率可达32 Gbit/s,平均吞吐率为20 Gbit/s,并且还有很大的提升潜力。该高速图像传输系统能够实现高吞吐率、高抗干扰、低错误率的图像数据传输,有助于各种不同视觉测量系统和图像处理系统的开发,具有广泛的应用价值。
Aiming at the issue of high-speed image data transmission among field programmable gate array( FPGA) chips in research and development of image acquisition and processing system; a full duplex high-speed image data transmission scheme with high throughput, high stability, and high anti-interference capability is designed. This inter-chip high-speed image transmission system provides a universal image transmission interface that is compatible with different data bit widths and user clock frequencies. The high-speed image transmission module is divided into a protocol layer and a physical layer. The protocol layer includes a cross-clock domain circuit and a CXP image transmission protocol encoding/decoding circuit to complete crossclock domain and encoding and decoding of image data stream; the physical layer based on the Aurora 8 B/10 B core completes the serial-parallel conversion of the data stream and multi-channel binding and other processing,and use GTH transceiver to achieve high-speed serial data receiving and sending. Simulation tests show that the image data transmission is correct,the image data flow synchronization clock is up to 250 MHz,the transmission bit width is up to 128 bit,the maximum throughput rate is up to32 Gbit/s,the average throughput rate is 20 Gbit/s,and a great potential for improvement still exists. The system can realize image data transmission with high throughput,high anti-interference,and low error rate,it is helpful for the development of various vision measurement systems and image processing systems,and has a wide range of application values.
Aiming at the issue of high-speed image data transmission among field programmable gate array( FPGA) chips in research and development of image acquisition and processing system; a full duplex high-speed image data transmission scheme with high throughput, high stability, and high anti-interference capability is designed. This inter-chip high-speed image transmission system provides a universal image transmission interface that is compatible with different data bit widths and user clock frequencies. The high-speed image transmission module is divided into a protocol layer and a physical layer. The protocol layer includes a cross-clock domain circuit and a CXP image transmission protocol encoding/decoding circuit to complete crossclock domain and encoding and decoding of image data stream; the physical layer based on the Aurora 8 B/10 B core completes the serial-parallel conversion of the data stream and multi-channel binding and other processing,and use GTH transceiver to achieve high-speed serial data receiving and sending. Simulation tests show that the image data transmission is correct,the image data flow synchronization clock is up to 250 MHz,the transmission bit width is up to 128 bit,the maximum throughput rate is up to32 Gbit/s,the average throughput rate is 20 Gbit/s,and a great potential for improvement still exists. The system can realize image data transmission with high throughput,high anti-interference,and low error rate,it is helpful for the development of various vision measurement systems and image processing systems,and has a wide range of application values.
引文
[1]唐瑞,姚远程,秦明伟.高速图像模拟源的研究与实现[J].自动化仪表,2017,38(8):40-44.
[2]于洋.基于FPGA的高速传输接口的设计与实现[D].武汉:华中科技大学,2007.
[3]李强.基于FPGA的高速低误码率传输系统的设计与实现[D].长沙:国防科学技术大学,2011.
[4]王松明.高速数据交换的FPGA实现[J].微型机与应用,2017,36(24):98-101.
[5]黄万伟,董永吉,陈博,等.Xilinx FPGA高速串行传输技术与应用[M].北京:电子工业出版社,2015.
[6]李维明,陈建军,陈星锜.基于Aurora协议的高速通信技术的研究[J].电子技术应用,2013,39(12):37-40.
[7]张清亮.基于FPGA高速通用串行接口的设计与应用[D].西安:西安电子科技大学,2015.
[8]潘国祯.基于FPGA实现的高速串口传输技术与实现[D].上海:复旦大学,2009.
[9]邓焰,戎蒙恬.基于FPGA的3.125Gbits串行通道设计实验[J].电子工师,2004(11):16-18.
[10]王艳秋,李旭,高锦春,等.基于CPRI协议的FPGA高速数据传输模块设计与实现[J].软件,2013,34(12):36-40.
[11]李元兵.通用高速信号处理平台设计及接口实现[D].绵阳:西南科技大学,2017.
[2]于洋.基于FPGA的高速传输接口的设计与实现[D].武汉:华中科技大学,2007.
[3]李强.基于FPGA的高速低误码率传输系统的设计与实现[D].长沙:国防科学技术大学,2011.
[4]王松明.高速数据交换的FPGA实现[J].微型机与应用,2017,36(24):98-101.
[5]黄万伟,董永吉,陈博,等.Xilinx FPGA高速串行传输技术与应用[M].北京:电子工业出版社,2015.
[6]李维明,陈建军,陈星锜.基于Aurora协议的高速通信技术的研究[J].电子技术应用,2013,39(12):37-40.
[7]张清亮.基于FPGA高速通用串行接口的设计与应用[D].西安:西安电子科技大学,2015.
[8]潘国祯.基于FPGA实现的高速串口传输技术与实现[D].上海:复旦大学,2009.
[9]邓焰,戎蒙恬.基于FPGA的3.125Gbits串行通道设计实验[J].电子工师,2004(11):16-18.
[10]王艳秋,李旭,高锦春,等.基于CPRI协议的FPGA高速数据传输模块设计与实现[J].软件,2013,34(12):36-40.
[11]李元兵.通用高速信号处理平台设计及接口实现[D].绵阳:西南科技大学,2017.