面向VLIW DSP处理器的智能汇编过程语法处理方案
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摘要
近年来高性能数字信号处理器(DSP)得到快速发展.高性能数字信号处理器处理任务所需的时间和能耗与对代码的指令级并行度的挖掘密切相关.为了获得高指令级并行度的代码,提高代码的可移植性,同时减轻软件开发人员的负担和减小编程的难度,我们提出了智能汇编这种抽象汇编程序解决方案来综合了高级语言和汇编语言两方面的优势.针对这种抽象汇编程序,需要智能汇编器这种面向高性能VLIW DSP硬件底层的优化编译器.智能汇编器是基于抽象的智能汇编过程进行代码优化的.本文提出了一种考虑高性能VLIW DSP硬件特性的智能汇编过程结构,并介绍了对这种智能汇编过程进行语法处理的方案和相应的核心算法以对这种过程和过程中的指令序列进行识别,能够为后续的代码优化环节提供过程和指令的语法信息.
High- performance digital signal processor( DSP) has developed quickly in recent years. The time and power expenses are closely related to the instruction level parallelism( ILP) of code. Under the consideration of combining the best of compiling and assembly,the intelligent assembly solution is capable of maintaining the ILP of code,improving the code portability and reducing the burden of developers. For intelligent assembly programs,corresponding assembler which is designed to the features of high- performance VLIW DSP is needed for code optimization. In this paper,an intelligent assembly procedure structure is presented together with corresponding syntax processing scheme. The algorithms for the recognizing of such a kind of procedure and its instruction list are introduced,which can provide syntax information of intelligent assembly procedures and instructions needed by the following code optimization phases in the assembler.
High- performance digital signal processor( DSP) has developed quickly in recent years. The time and power expenses are closely related to the instruction level parallelism( ILP) of code. Under the consideration of combining the best of compiling and assembly,the intelligent assembly solution is capable of maintaining the ILP of code,improving the code portability and reducing the burden of developers. For intelligent assembly programs,corresponding assembler which is designed to the features of high- performance VLIW DSP is needed for code optimization. In this paper,an intelligent assembly procedure structure is presented together with corresponding syntax processing scheme. The algorithms for the recognizing of such a kind of procedure and its instruction list are introduced,which can provide syntax information of intelligent assembly procedures and instructions needed by the following code optimization phases in the assembler.
引文
[1]B.Li and G.Chen.Computer organization and system structure[M].Beijing:Higher Education Press,2010.
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[4]邓春华,安虹,路璐,王耀彬.分片式处理器上的谓词执行技术优化[J].小型微型计算机系统,2012,33(2):399-403.
[5]K.Zhang,S.Chen,H.Chen,Y.Wang,X.Chen,S.Liu and W.Liu.CMRF:A Configurable Matrix Register File for Accelerating Matrix Operations on SIMD Processors[J].IEICE Electronics Express 2012,9(4):283-289.
[6]S.Chen,J.Wang,J.Lu,et al.YHFT-QDSP:High-Performance Heterogeneous Multi-Core DSP[J].Journal of Computer Science and Technology 2010,25(2):214-224.
[7]H.Chen and H.Huang.Design and implementation of YHFT-DSP simulation platform based on EBus[J].Journal of Computer Applications,2011,31(4):1129-1132.
[8]SHU Sheng-liang,SUN Yong-jie,WAN Jiang-hua.Design and implementation of an interrupter processing system in Matrix DSPs[J].Computer Engineering&Science.2012,34(1):64-68.
[9]甄扬.基于多核VLIW DSP的数字信号变换函数并行优化[D].安徽:中国科学技术大学,2015.
[10]Texas Instruments Incorporated.TMS320C6000seris DSP programming tools and handbook[M].Beijing:Tsinghua University Press,2006.
[11]S.S.Muchnick.Advanced Compiler Design and Implementation[M].Elsevier Science Ltd,2005.
[12]Yonghua Hu,Shuming chen,Jie Huang.Preprocessing scheme of intelligent assembly for a high performance VLIW DSP[J].CGC 2012,187-190.
[2]C.Zhang,Z.Wang,C,Zhang,K.Dai,and X.Xiao.Computer architeture,2nd ed[M].Beijing:Tsinghua University Press,2005.
[3]杨旭,何虎,孙义和.分簇VLIW结构下利用数据依赖图优化调度的研究[J].计算机学报,2011,34(1):182-192.
[4]邓春华,安虹,路璐,王耀彬.分片式处理器上的谓词执行技术优化[J].小型微型计算机系统,2012,33(2):399-403.
[5]K.Zhang,S.Chen,H.Chen,Y.Wang,X.Chen,S.Liu and W.Liu.CMRF:A Configurable Matrix Register File for Accelerating Matrix Operations on SIMD Processors[J].IEICE Electronics Express 2012,9(4):283-289.
[6]S.Chen,J.Wang,J.Lu,et al.YHFT-QDSP:High-Performance Heterogeneous Multi-Core DSP[J].Journal of Computer Science and Technology 2010,25(2):214-224.
[7]H.Chen and H.Huang.Design and implementation of YHFT-DSP simulation platform based on EBus[J].Journal of Computer Applications,2011,31(4):1129-1132.
[8]SHU Sheng-liang,SUN Yong-jie,WAN Jiang-hua.Design and implementation of an interrupter processing system in Matrix DSPs[J].Computer Engineering&Science.2012,34(1):64-68.
[9]甄扬.基于多核VLIW DSP的数字信号变换函数并行优化[D].安徽:中国科学技术大学,2015.
[10]Texas Instruments Incorporated.TMS320C6000seris DSP programming tools and handbook[M].Beijing:Tsinghua University Press,2006.
[11]S.S.Muchnick.Advanced Compiler Design and Implementation[M].Elsevier Science Ltd,2005.
[12]Yonghua Hu,Shuming chen,Jie Huang.Preprocessing scheme of intelligent assembly for a high performance VLIW DSP[J].CGC 2012,187-190.