一种新型存储器测试辅助分析方法
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摘要
为了解决存储器测试数据映射到失效存储单元效率较低且精确度不够的问题,本文提出一种存储器测试辅助分析的方法:首先通过修改存储器编译器(memory compiler),使其自动生成存储阵列版图的物理坐标文件(bitmap).然后将测试得到的存储单元的失效信息在已生成的坐标文件中进行寻址,找出被测试失效单元位于版图中的具体物理坐标.最后通过得到的坐标信息自动输出该失效存储单元的译码信息及该存储单元位于整个存储阵列中的物理坐标二维图像.
In order to solve the problem that the memory test data is mapped to specific failed cells with low efficiency and insufficient precision,this paper proposes a memory test-assisted analysis method.Firstly,the memory compiler will automatically generate the physical coordinate file of the storage array map after modifying it.Then the failure information of the storage unit is addressed in the generated coordinate file to find out the physical coordinates of the failure storage unit in the map.Finally,through the information of coordinate,the decoding information of the failed storage unit will be automatically output,as well as the physical coordinate two-dimensional image(of the failed storage unit)located in the entire storage array.
In order to solve the problem that the memory test data is mapped to specific failed cells with low efficiency and insufficient precision,this paper proposes a memory test-assisted analysis method.Firstly,the memory compiler will automatically generate the physical coordinate file of the storage array map after modifying it.Then the failure information of the storage unit is addressed in the generated coordinate file to find out the physical coordinates of the failure storage unit in the map.Finally,through the information of coordinate,the decoding information of the failed storage unit will be automatically output,as well as the physical coordinate two-dimensional image(of the failed storage unit)located in the entire storage array.
引文
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[2]王仁平,魏榕山,高扬标,等.优化芯片面积的标准单元库改进[J].福州大学学报(自然科学版),2017,45(1),98-101.
[3]张亚灵,徐东明.一种基于CMOS工艺的掩模ROM设计[J].西安邮电学院学报,2009,(1):101-104.
[4]邹文英,徐新宇,徐睿.一款深亚微米ASIC芯片的后端设计[J].电子与封装,2012,12(8):26-29.
[5]姚其爽.高速低功耗嵌入式SRAM研究与设计[D].西安:西北工业大学,2007.
[6] O'Neil P E.Model 204architecture and perfo-rmance[C].In:Proceedings of the 2ndInternatio-nal Workshop on High Performance Transacti-on Systems.London,UK:Springer 1987,40-59.
[7] O'Neil P E.Quass D.Improved query perfor-mance with variant indexes[C].ACM SIGMOD R-ecord,1997,26(2):38-49.
[8] VanSchaik S J,de Moor O.A memory effic-ient reachability data structure through bit vec-tor compression[C].In:Proceedings of the 2011ACM SIGMOD International Conference on M-anagement of Data.Athens,Greece:ACM,2011.913-924.
[9]龚展立.面向嵌入式SOC的Memory Compiler设计与实现[D].合肥:安徽大学,2012.
[10] Mentor Graphics Corporation.Tessent Silicon-Insight User's Manual for Tessent Shell[EB/OL].(2017-03)[2018-06].http:∥go.mentor.com/539_o