粗粒度可重构SoC层次化配置存储器设计
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摘要
配置信息的生成效率与质量直接影响着粗粒度可重构SoC结构的运行效果.传统的方法将配置信息作为一个整体存储器,每个处理单元在需要配置信息时都要从该存储器读取配置信息,运行效率低下且功耗较大.为降低配置信息生成方法的功耗,设计了一种低功耗层次式的配置信息存储器结构,将配置信息分为相互独立的操作配置信息和互连配置信息存储器两部分,实现了不同层次上的重构,最后根据上下文优化配置信息生成.实验结果表明:在运行性能不变的情况下,提出的配置信息生成方法功耗可以减少23.7%~32.6%.同时,由于操作和互连配置信息相分离,使得每次需要配置的存储器容量较小,在配置速度和性能上也有很大的优势.
The generate efficiency and quality of configuration information directly affect the operation effect of the coarse grained reconfigurable SoC.Since the traditional approach treats the configuration memory as a whole,and each processing unit needs to read configuration information from the memory,the operation efficiency is low and the power consumption is large.In this paper,a low power hierarchical configuration information storage architecture is designed, which divides configuration information into separate operating configuration information and interconnect configuration information,and then generates the configuration information based on the context.Experimental results show that the configuration information generation method proposed in this paper can reduce power consumption of 23.7%-32.6% while keeping the same performance.At the same time,because of the separation of the operation and the configuration information,the configuration information capacity is small,so it has a great advantage in configuration speed and performance.
The generate efficiency and quality of configuration information directly affect the operation effect of the coarse grained reconfigurable SoC.Since the traditional approach treats the configuration memory as a whole,and each processing unit needs to read configuration information from the memory,the operation efficiency is low and the power consumption is large.In this paper,a low power hierarchical configuration information storage architecture is designed, which divides configuration information into separate operating configuration information and interconnect configuration information,and then generates the configuration information based on the context.Experimental results show that the configuration information generation method proposed in this paper can reduce power consumption of 23.7%-32.6% while keeping the same performance.At the same time,because of the separation of the operation and the configuration information,the configuration information capacity is small,so it has a great advantage in configuration speed and performance.
引文
[1]Kim Y,Park I,Choi K,et al.Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture[C]//Proc of the 2006Int Symp on Low Power Electronics and Design.New York:ACM,2006:310-315
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[4]Guo Y.Mapping applications to a coarse-grained reconfigurable architecture[D].Enschede,Overijssel,Netherlands:University of Twente,2006
[5]Shen Jianliang.Research on the design methodology of application specific coarse grained reconfigurable system on chip[D].Changsha:National University of Defense Technology,2014(in Chinese)(沈剑良.应用定制的粗粒度可重构SoC设计方法研究[D].长沙:国防科学技术大学,2014)
[6]Rauwerda G K,Heysters P M,Smit G J M.Towards software defined radios using coarse-grained reconfigurable hardware[J].IEEE Trans on Very Large Scale Integration Systems,2008,16(1):3-13
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[10]Zuo Yanhui.Research on compiler for coarse grained reconfigurable array processor[D].Changsha:National University of Defense Technology,2008(in Chinese)(左艳辉.粗粒度可重构阵列处理器编译工具研究[D].长沙:国防科学技术大学,2008)
[11]Zhu Min,Liu Leibo,Yin Shouyi.Timing parameter analysis of critical loop to reconfigurable array mapping[J].Journal of Computer Engineering,2012,38(22):260-262(in Chinese)(朱敏,刘雷波,尹首一.关键循环到可重构阵列映射中的时序参数分析[J].计算机工程,2012,38(22):260-262)
[12]Yang Xiaohui,Dai Zibin,Zhang Yongfu.Research and design of reconfigurable computing targeted at block CipherProcessing[J].Journal of Computer Research and Development,2009,46(6):962-967(in Chinese)(杨晓辉,戴紫彬,张永福.可重构分组密码处理结构模型研究与设计[J].计算机研究与发展,2009,46(6):962-967)
[13]Garcia A,Berekovic M,Aa T V.Mapping of the AES cryptographic algorithm on a coarse-grain reconfigurable array processor[C]//Proc of Int Conf on Application-Specific Systems,Architectures and Processors.Los Alamitos,CA:IEEE Computer Society,2008:245-250
[14]Veredas F J,Scheppler M,Moffat W,et al.Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes[C]//Proc of the 15th Int Conf on Field Programmable Logic and Applications.Piscataway,NJ:IEEE,2005:106-111
[15]Yoon J W,Shrivastava A,Park S,et al.A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures[J].IEEE Trans on Very Large Scale Integration Systems,2009,17(11):1565-1578
[16]Lee G,Lee S,Choi K,et al.Routing-aware application mapping considering steiner points for coarse-grained reconfigurable architecture[C]//Proc of Int Symp on Applied Reconfigurable Computing.Berlin:Springer,2010:231-243
[2]Ye Z A,Moshovos A,Hauck S,et al.CHIMAERA:A high-performance architecture with a tightly-coupled reconfigurable functional unit[C]//Proc of Annual Int Symp on Computer Architecture.New York:ACM,2000:225-235
[3]Lee J E,Choi K,Dutt N D.Compilation approach for coarse-grained reconfigurable architectures[J].IEEE Design&Test of Computers,2003,20(1):26-33
[4]Guo Y.Mapping applications to a coarse-grained reconfigurable architecture[D].Enschede,Overijssel,Netherlands:University of Twente,2006
[5]Shen Jianliang.Research on the design methodology of application specific coarse grained reconfigurable system on chip[D].Changsha:National University of Defense Technology,2014(in Chinese)(沈剑良.应用定制的粗粒度可重构SoC设计方法研究[D].长沙:国防科学技术大学,2014)
[6]Rauwerda G K,Heysters P M,Smit G J M.Towards software defined radios using coarse-grained reconfigurable hardware[J].IEEE Trans on Very Large Scale Integration Systems,2008,16(1):3-13
[7]Venkataramani G,Najjar W,Kurdahi F,et al.A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture[C]//Proc of Int Conf on Compilers,Architecture,and Synthesis for Embedded Systems.New York:ACM,2001:116-125
[8]Lee J,Choi K,Dutt N D.An algorithm for mapping loops onto coarse-grained reconfigurable architectures[J].ACM Sigplan Notices,2003,38(7):183-188
[9]Dmuroulakos G,Galanis M H D,Goutis C E.Optimized back-end compiler techniques for mapping applications on coarse-grained reconfigurable matrices[J].World Scientific and Engineering Academy and Society Trans on Computers,2007,6(1):181-188
[10]Zuo Yanhui.Research on compiler for coarse grained reconfigurable array processor[D].Changsha:National University of Defense Technology,2008(in Chinese)(左艳辉.粗粒度可重构阵列处理器编译工具研究[D].长沙:国防科学技术大学,2008)
[11]Zhu Min,Liu Leibo,Yin Shouyi.Timing parameter analysis of critical loop to reconfigurable array mapping[J].Journal of Computer Engineering,2012,38(22):260-262(in Chinese)(朱敏,刘雷波,尹首一.关键循环到可重构阵列映射中的时序参数分析[J].计算机工程,2012,38(22):260-262)
[12]Yang Xiaohui,Dai Zibin,Zhang Yongfu.Research and design of reconfigurable computing targeted at block CipherProcessing[J].Journal of Computer Research and Development,2009,46(6):962-967(in Chinese)(杨晓辉,戴紫彬,张永福.可重构分组密码处理结构模型研究与设计[J].计算机研究与发展,2009,46(6):962-967)
[13]Garcia A,Berekovic M,Aa T V.Mapping of the AES cryptographic algorithm on a coarse-grain reconfigurable array processor[C]//Proc of Int Conf on Application-Specific Systems,Architectures and Processors.Los Alamitos,CA:IEEE Computer Society,2008:245-250
[14]Veredas F J,Scheppler M,Moffat W,et al.Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes[C]//Proc of the 15th Int Conf on Field Programmable Logic and Applications.Piscataway,NJ:IEEE,2005:106-111
[15]Yoon J W,Shrivastava A,Park S,et al.A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures[J].IEEE Trans on Very Large Scale Integration Systems,2009,17(11):1565-1578
[16]Lee G,Lee S,Choi K,et al.Routing-aware application mapping considering steiner points for coarse-grained reconfigurable architecture[C]//Proc of Int Symp on Applied Reconfigurable Computing.Berlin:Springer,2010:231-243