SOI工艺抗辐照SRAM型FPGA设计与实现
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摘要
为提升SRAM型FPGA电路块存储器和配置存储器抗单粒子翻转性能,本文提出一种脉冲屏蔽SRAM单元结构。该结构通过在标准的六管单元中加入延迟结构,增大单元对单粒子事件响应时间,实现对粒子入射产生的脉冲电流屏蔽作用。以64k SRAM作为验证电路进行单粒子翻转性能对比,电路的抗单粒子翻转阈值由采用标准六管单元的抗单粒子翻转阈值大于25 Me V·cm2·mg-1提升至大于45 Me V·cm2·mg-1,加固单元面积较标准六管单元增大约21.3%。30万门级抗辐照FPGA电路通过脉冲屏蔽单元结合抗辐照SOI工艺实现,其抗辐照指标分别为:抗单粒子翻转阈值大于37.3 Me V·cm2·mg-1,抗单粒子锁定阈值大于99.8 Me V·cm2·mg-1,抗电离总剂量能力大于200 krad(Si)。
A pulse shielded SRAM cell is proposed for increasing the SEU performance which is used in block RAM( BRAM) and configuration memory of FPGAs. The pulse current from an incident particle is shielded because of the increasing single event response time for a SRAM cell. The SEU performance is verified by the 64 k SRAMs with SEU threshold improving from 25 Me V·cm~2·mg~(-1) to 45 Me V·cm~2·mg~(-1) at only 21. 3% additional cost of the SRAM cell area. By adopting the pulse shielded SRAM cell and radiation hardened process,the 300,000-gate FPGA possesses radiation features: SEU threshold higher than 37. 3 Me V · cm~2·mg~(-1); SEL threshold higher than 99. 8 Me V·cm~2·mg~(-1) and total dose tolerance higher than 200 krad( Si) respectively.
A pulse shielded SRAM cell is proposed for increasing the SEU performance which is used in block RAM( BRAM) and configuration memory of FPGAs. The pulse current from an incident particle is shielded because of the increasing single event response time for a SRAM cell. The SEU performance is verified by the 64 k SRAMs with SEU threshold improving from 25 Me V·cm~2·mg~(-1) to 45 Me V·cm~2·mg~(-1) at only 21. 3% additional cost of the SRAM cell area. By adopting the pulse shielded SRAM cell and radiation hardened process,the 300,000-gate FPGA possesses radiation features: SEU threshold higher than 37. 3 Me V · cm~2·mg~(-1); SEL threshold higher than 99. 8 Me V·cm~2·mg~(-1) and total dose tolerance higher than 200 krad( Si) respectively.
引文
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[12]Sterpone L,Boragno L.Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs[C].2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design(IOLTS),Thessaloniki,Greece,July 3-5,2017.
[13]Lima F,Carro L,Reis R.Reducing pin and area overhead in fault-tolerant FPGA-based designs[C].Proceedings of The 2013ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays,California,USA,February 23-25,2003.
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[17]Haque K,Beckett P.Radiation-hard field-programmable gate arrays configuration technique using silicon on sapphire[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2014,22(2):232-241.
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[19]Tonfat J,Lima F K,Rech P,et al.Analyzing the effectiveness of a frame-level redundancy scrubbing technique for SRAM-based FPGAs[J].IEEE Transactions on Nuclear Science,2015,62(6):3080–3087.
[20]Liu S T,Nelson D K,Tsang J K,et al.The effect of active delay element resistance on limiting heavy ion SEU upset cross-sections of SOI ADE/SRAMs[J].IEEE Transactions on Nuclear Science,2007,54(6):2480-2487.
[21]Rockett L R.Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors[J].IEEE Transactions on Nuclear Science,1992,39(5):1532-1541.
[22]Ochoa A,Axness C L,Weaver H T,et al.A proposed new structure for SEU immunity in SRAM employing drain resistance[J].IEEE Electron Device Letters,1987,8(11):537-539.
[23]QJ 10005-2008,宇航用半导体器件重离子单粒子效应试验指南[S].
[24]Renovell M.SRAM-Based FPGAs:a structural test approach[C].Proceedings.XI Brazilian Symposium on Integrated Circuit Design,Rio de Janeiro,Brazil,October 3,1998.
[25]Liao Y B,Li P,Ruan A W,et al.Full coverage manufacturing testing for SRAM-based FPGA[C].Proceedings of the 200912th International Symposium on Integrated Circuits,Singapore,Singapore,December 14-16,2009.
[26]Renovell M,Portal J M,Figueras J,et al.Testing the interconnect of RAM-based FPGAs[J].IEEE Design&Test of Computers,1998,15(1):45-50.
[27]Renovell M,Figueras J,Zorian Y.SRAM-based FPGA’s:testing the LUT/RAM modules[C].Proceedings International Test Conference 1998,Washington,DC,USA,October 18-23,1998.
[28]QJ 10004—2008,宇航用半导体器件总剂量辐照试验方法[S].
[2]Tonfat J,Lima F K,Artola L,et al.Analyzing the influence of the angles of incidence on SEU and MBU events induced by low LET heavy ions in a 28-nm SRAM-based FPGA[C].201616th European Conference on Radiation and Its Effects on Components and Systems(RADECS),Bremen,Germany,September 19-23,2016.
[3]Ostler P S,Caffrey M P,Gibelyou D S,et al.SRAM FPGA reliability analysis for harsh radiation environments[J].Transactions on Nuclear Science,2009,56(6):3519-3526.
[4]Glein R,Rittner F,Becher A.Reliability of space-grade vs.cots SRAM-Based FPGA in n-modular redundancy[C].2015NASA/ESA Conference on Adaptive Hardware and Systems(AHS),Montreal,QC,Canada,June 15-18,2015.
[5]Tambara L A,Tonfat J L,Reis R,et al.Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects[C].2014 15th Latin American Test Workshop(LATW),Fortaleza,Brazil,March 12-15,2014.
[6]宋凝芳,朱明达,潘雄.SRAM型FPGA单粒子效应试验研究[J].宇航学报,2012,33(6):836-842.[Song Ning-fang,Zhu Ming-da,Pan Xiong.Experimental study of single event effects in SRAM-Based FPGA[J].Journal of Astronautics.2012,33(6):836-842.]
[7]邢克飞,杨俊,王跃科,等.Xilinx SRAM型FPGA抗辐射设计技术研究[J].宇航学报,2007,28(1):123-151.[Xing Ke-fei,Yang Jun,Wang Yue-ke,et al.Study on the antiradiation technique for Xilinx SRAM-Based FPGA[J].Journal of Astronautics.2007,28(1):123-151.]
[8]Schwank J R,Cavrois F V,Shaneyfelt M R,et al.Radiation effects in SOI technologies[J].IEEE Transactions on Nuclear Science,2003,50(3):522-538.
[9]Xilinx,Inc.Virtex 2.5V field programmable gate arrays Xilinx product specification DS003-1[EB/OL].2013[2018].https://china.xilinx.com/support/documentation/data_sheets/ds003.pdf.
[10]Wang J J,Katz B R,Sun J S,et al.SRAM based reprogrammable FPGA for space applications[J].IEEE Transactions on Nuclear Science,1999,46(6):1728-1735.
[11]Xilinx,Inc.Triple module redundancy design techniques for Virtex FPGAs[EB/OL].2006[2018].http://www.xilinx.com/support/documentation/application_notes/xapp197.pdf.
[12]Sterpone L,Boragno L.Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs[C].2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design(IOLTS),Thessaloniki,Greece,July 3-5,2017.
[13]Lima F,Carro L,Reis R.Reducing pin and area overhead in fault-tolerant FPGA-based designs[C].Proceedings of The 2013ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays,California,USA,February 23-25,2003.
[14]Xilinx,Inc.Correcting single-event upsets through Virtex partial configuration.[EB/OL].2001[2018].https://www.xilinx.com/support/documentation/application_notes/xapp216.pdf.
[15]Alzu H I,Vallejo L M.Design techniques for Xilinx Virtex FPGA configuration memory scrubbers[J].IEEE Transactions on Nuclear Science,2013,60(1):376–385.
[16]Wirthlin M,Rollins N,Caffrey M,et al.Hardness by design techniques for field programmable gate arrays[C].The 11th Annual NASA Symposium on VLSI Design,Idaho,USA,May 28-29,2003.
[17]Haque K,Beckett P.Radiation-hard field-programmable gate arrays configuration technique using silicon on sapphire[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2014,22(2):232-241.
[18]Kumar M,Digdarsini D,Misra N.SEU mitigation of rad-tolerant Xilinx FPGA using external scrubbing for geostationary mission[C].2017 4th International Conference on Signal Processing and Integrated Networks(SPIN),Noida,India,February 2-3,2017.
[19]Tonfat J,Lima F K,Rech P,et al.Analyzing the effectiveness of a frame-level redundancy scrubbing technique for SRAM-based FPGAs[J].IEEE Transactions on Nuclear Science,2015,62(6):3080–3087.
[20]Liu S T,Nelson D K,Tsang J K,et al.The effect of active delay element resistance on limiting heavy ion SEU upset cross-sections of SOI ADE/SRAMs[J].IEEE Transactions on Nuclear Science,2007,54(6):2480-2487.
[21]Rockett L R.Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors[J].IEEE Transactions on Nuclear Science,1992,39(5):1532-1541.
[22]Ochoa A,Axness C L,Weaver H T,et al.A proposed new structure for SEU immunity in SRAM employing drain resistance[J].IEEE Electron Device Letters,1987,8(11):537-539.
[23]QJ 10005-2008,宇航用半导体器件重离子单粒子效应试验指南[S].
[24]Renovell M.SRAM-Based FPGAs:a structural test approach[C].Proceedings.XI Brazilian Symposium on Integrated Circuit Design,Rio de Janeiro,Brazil,October 3,1998.
[25]Liao Y B,Li P,Ruan A W,et al.Full coverage manufacturing testing for SRAM-based FPGA[C].Proceedings of the 200912th International Symposium on Integrated Circuits,Singapore,Singapore,December 14-16,2009.
[26]Renovell M,Portal J M,Figueras J,et al.Testing the interconnect of RAM-based FPGAs[J].IEEE Design&Test of Computers,1998,15(1):45-50.
[27]Renovell M,Figueras J,Zorian Y.SRAM-based FPGA’s:testing the LUT/RAM modules[C].Proceedings International Test Conference 1998,Washington,DC,USA,October 18-23,1998.
[28]QJ 10004—2008,宇航用半导体器件总剂量辐照试验方法[S].