对FPGA配置码点软错误敏感性的细粒度研究（英文）
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摘要
本文对Xilinx的Virtex-4器件的配置存储器(Configuration RAM,CRAM)做了详尽的错误注入实验.并给出了适用于Virtex-4的逻辑资源与码流对应关系的详细信息,利用这些信息对实验结果进行分析可以找出对电路可靠性影响最大的配置码点.本文用了两种错误模型来评估电路的可靠性,一个模型用来评估持续存在的错误的影响,另一个模型用来评估瞬时错误对应用了重刷写技术的电路的影响.对实验结果的详尽分析为用于FPGA的容错技术的研究提供了新的数据支持.本文的主要贡献包括一个能够进行细粒度定位错误注入的平台、对CRAM中码点翻转造成的影响的详细分析、两个用于评估CRAM中码点翻转效应的指标以及对利用错误注入的数据进行容错技术加强的方法.
This paper presents the results of an extensive fault injection campaign performed on the configuration RAM(CRAM)of Xilinx Virtex-4 devices.It presents new information about the mapping of the bits within the frames and uses this information to identify the bits that are most sensitive.Two fault models are used,one which models continuous faults and the other which models transitory faults for designs with a background scrub.The fine-grained analysis of the results provides valuable new data for researchers investigating FPGA protection techniques.The main contributions of this paper include a fault injection platform,a fine-grained and analytic study of the impact of CRAM upsets,two metrics for assessing the impact of CRAM upsets and a demonstration of how existing FPGA mitigation techniques can be enhanced using fault injection data.
This paper presents the results of an extensive fault injection campaign performed on the configuration RAM(CRAM)of Xilinx Virtex-4 devices.It presents new information about the mapping of the bits within the frames and uses this information to identify the bits that are most sensitive.Two fault models are used,one which models continuous faults and the other which models transitory faults for designs with a background scrub.The fine-grained analysis of the results provides valuable new data for researchers investigating FPGA protection techniques.The main contributions of this paper include a fault injection platform,a fine-grained and analytic study of the impact of CRAM upsets,two metrics for assessing the impact of CRAM upsets and a demonstration of how existing FPGA mitigation techniques can be enhanced using fault injection data.
引文
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[2]MUKHERJEE S.Device and circuit level modeling measurement and mitigtion[M].Burlington,M A,USA:Morgan Kaufmann,2011:43-79.
[3]KRISHNASWAMY S,PLAZA S M,MARKOV I L,et al.Enhancing design robustness with reliabilityaware resynthesis and logic simulation[C]∥Proceedings of the 2007IEEE/ACM International conference on Computer-Aided Design.San Jose,CA,USA:IEEE Press,2007:149-154.
[4]PRATT B,CAFFREY M,CARROLL J F,et al.Fine-grain SEU mitigation for FPGAs using partial TMR[J].IEEE Transactions on Nuclear Science,2008,55(4):2274-2280.
[5]MORGAN K,CAFFREY M,GRAHAM P,et al.SEU-induced persistent error propagation in FPGAs[J].IEEE Transactions on Nuclear Science,2005,52(6):2438-2445.
[6]JING N,LEE J Y,FENG Z,et al.SEU fault evaluation and characteristics for SRAM-based FPGAarchitectures and synthesis algorithms[J].ACM Transactions on Design Automation of Electronic Systems,2013,18(1):13.
[7]HU Y,FENG Z,HE L,et al.Robust FPGA resynthesis based on fault-tolerant Boolean matching[C]∥Proceedings of the 2008IEEE/ACM International Conference on Computer-Aided Design.San Jose,CA,USA:IEEE Press,2008:706-713.
[8]FENG Z,HU Y,HE L,et al.IPR:in-place reconfiguration for FPGA fault tolerance?[C]∥Proceedings of the2009International Conference on Computer-Aided Design.San Jose,CA,USA:ACM,2009:105-108.
[9]LEE J Y,FENG Z,HE L.In-place decomposition for robustness in FPGA[C]∥Proceedings of the International Conference on Computer-Aided Design.San Jose,CA,USA:IEEE Press,2010:143-148.
[10]JING N,LEE J Y,HE W,et al.Mitigating FPGA interconnect soft errors by in-place LUT inversion[C]∥Proceedings of the International Conference on Computer-Aided Design.San Jose,CA,USA:IEEE Press,2011:582-586.
[11]BERNARDI P,REORDA M S,STERPONE L,et al.On the evaluation of SEU sensitiveness in SRAM-based FPGAs[C]∥On-Line Testing Symposium,2004.IOLTS 2004.Proceedings.10th IEEEInternational.Funchal,Madeira Island,Portugal:IEEE Press,2004:115-120.
[12]WANG Z M,YAO Z B,GUO H X,et al.Bitstream decoding and SEU-induced failure analysis in SRAM-based FPGAs[J].Science China Information Sciences,2012,55(4):971-982.
[13]SCHUMACHER P.SEU emulation environment[D/OL].(2012-04-09).[2016-12-29].http:∥www.xilinx.com/support/documentation/white_papers/wp414-SEU-Emulation.pdf.
[14]XILINX INC.Virtex-4FPGA User Guide[EB/OL].(2008-12-1).[2017-2-8].http:∥www.xilinx.com/.
[15]LAVIN C,PADILLA M,LUNDRIGAN P,et al.RapidSmith:A Library for Low-level Manipulation of Partially Placed-and-Routed FPGA Designs[EB/OL].(2014-1-24)[2017-2-8].http:∥rapidsmith.sourceforge.net.
[16]BETZ V,ROSE J,MARQUARDT A.Routing tools and routing architecture generation[M].Berlin,Germany:Springer Science&Business Media,2012:63-103.
[17]XILINX INC.Virtex-4FPGA Configuration User Guide[EB/OL].(2009-6-9).[2017-2-8].http:∥www.xilinx.com/.
[18]ITURBE X,AZKARATE M,MARTINEZ I,et al.A novel SEU,MBU and SHE handling strategy for Xilinx Virtex-4FPGAs[C]∥2009International Conference On Field Programmable Logic and Applications.Pragne,Czech Republic:IEEE Press,2009:569-573.
[19]LEE J Y,CHANG C R,JING N,et al.Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs[C]∥2012International Conference On Field-Programmable Technology(FPT).Seoul,South Korea:IEEE Press,2012:23-28.
[20]BRGLEZ F.ACM/SIGDA Benchmark Electronic Newsletter DAC 93Edition[R/OL].(1993-2-1)1993.[2017-2-8].http:∥www.cse.wustl.edu/~jain/cse567-08/ftp/fpga/#Brglez93.
[21]OPENCORES.ORG.the#1community within open source hardware IP-cores[R/OL].(2016-10-8)[2017-2-8].http:∥opencores.org/.
[22]ALDERIGHI M,CASINI F,D'ANGELO S,et al.A preliminary study about SEU effects on programmable interconnections of SRAM-based FPGAs[J].Journal of Electronic Testing,2013,29(3):341-350.
[23]XILINX INC.Xilinx PG036Soft Error Mitigation Controller,LogiCORE IP Product Guide[EB/OL].(2015-9-30).[2017-2-8].http:∥www.xilinx.com/.