一种路由交换阵列节点芯片及其系统的设计与实现
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摘要
介绍一种面向大数据处理数据中心应用的计算/控制/网络存储的路由交换阵列节点芯片及其所组成的安全交换阵列原型机的设计与实现;该路由交换阵列系统通过因特网远程使用软件定义网络(SDN)方式对高速安全交换网络的内部路由控制和安全等模块进行集中编程控制,满足数据中心对数据传输带宽容量的需求;同时并行计算过程中消除网络传输瓶颈,避免了数据中心网络等资源的长期占用浪费,为下一代数据中心解决方案的形成打下基础。另外还简述了其在金融交易系统领域大数据应用尝试的研究近况。
We introduce an application in network computing/control/storage network,including a node controller chip of routing &switching array and a prototype design and implementation.The routing &switching array system uses software defined network(SDN)through the Internet to realize the integrated programming control on the inner routing control and security module of the high speed secure switching network,so as to meet the need of the data center for data transmission bandwidth capacity.Besides,we alleviate and eliminate the bottleneck of network transmission of the parallel computing process,thus avoiding the waste of long-term occupation of network data center resources and laying a foundation for the solutions of next generation data centers.In addition,we briefly introduce the current research situation of its application in the financial transaction system.
We introduce an application in network computing/control/storage network,including a node controller chip of routing &switching array and a prototype design and implementation.The routing &switching array system uses software defined network(SDN)through the Internet to realize the integrated programming control on the inner routing control and security module of the high speed secure switching network,so as to meet the need of the data center for data transmission bandwidth capacity.Besides,we alleviate and eliminate the bottleneck of network transmission of the parallel computing process,thus avoiding the waste of long-term occupation of network data center resources and laying a foundation for the solutions of next generation data centers.In addition,we briefly introduce the current research situation of its application in the financial transaction system.
引文
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[2]Wu Yi-fei,Ren Zhi-gang,Feng Ying,et al.Analysis of fault arc in high-speed switch applied in hybrid circuit breaker[J].Plasma Science and Technology,2016,18(3):299-304.
[3]Wu Li-ji,Ji Ying-jie,Zhang Xiang-min,et al.Design of anti power attack AES algorithm engine for high speed network security co processor[J].Journal of Tsinghua University(Natural Science Edition),2009(S2):2097-2102.(in Chinese)
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[5]Qin Ji-long,Li Qing-hua,Wang En-dong,et al.Realization and design a cloud storage device of cloud safety[C]∥Proc of2014HPC China 2014 Conference,2014:913-917.(in Chinese)
[6]Li Qing-hua,Qin Ji-long,Ding Xu,et al.An on-chip Interconnection QoS verification platform of processor of large data for architectural modeling analysis[C]∥Proc of ICYCSEE2015,2015:439-447.(in Chinese)
[7]Santos A,Fernandes S,Antonello R,et al.High-performance traffic workload architecture for testing DPI systems[C]∥Global Telecommunications Conference(GLOBECOM2011),2011:1-5.
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