LOD效应和WPE效应在纳米工艺PDK中的应用
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摘要
本文研究了自主开发的40nm工艺PDK中的LOD效应和WPE效应.LOD参数SA和WPE参数left影响CMOS器件特性,尤其饱和电流I_(dsat)和阈值电压VTH.随着SA减小,NMOS的I_(dsat)减小4.25%而VTH增大2.79%;PMOS的电参数与SA关系曲线与NMOS的一致,但比NMOS趋势要强,I_(dsat)减小8.32%而VTH增大6.78%;并解释了LOD效应的物理机制.随着left的减小,NMOS的I_(dsat)减小9.03%而VTH增大12.5%;PMOS的电参数与left关系曲线比NMOS的要弱,I_(dsat)减小8.50%而VTH增大4.61%,并提出了WPE效应下器件电参数变化原因.在纳米工艺PDK中,LOD效应和WPE效应的准确应用可以更好地模拟器件性能并改善电路设计精度.
In this paper,We research LOD and WPE effects of self-developed 40 nm process PDK.The parameter SA of LOD effect and the parameter left of WPE effect influence the characteristics of CMOS device,especially the saturation current I_(dsat)and the threshold voltage VTH.With the decrease of SA,I_(dsat)of NMOS decreases by 4.25%and VTHincreases by 2.79%.The relationship between electrical parameters and SA of PMOS is consistent with that of NMOS,but the trend is stronger than NMOS,I_(dsat)decreases by 8.32% and VTHincreases by 6.78%.The physical mechanism of LOD effect is explained.With the decrease of left,the I_(dsat)of NMOS decreases by 9.03%and VTHincreases by 12.5%.The relationship between the electrical parameters of PMOS and left is weaker than that of NMOS,I_(dsat)decreases by 8.50%,and VTHincreases by 4.61%.The cause that the electrical parameters change under WPE effect is proposed.In the nanometer process PDK,the accurate application of LOD and WPE effects can better simulate device performance,and improve the precision of circuit.
In this paper,We research LOD and WPE effects of self-developed 40 nm process PDK.The parameter SA of LOD effect and the parameter left of WPE effect influence the characteristics of CMOS device,especially the saturation current I_(dsat)and the threshold voltage VTH.With the decrease of SA,I_(dsat)of NMOS decreases by 4.25%and VTHincreases by 2.79%.The relationship between electrical parameters and SA of PMOS is consistent with that of NMOS,but the trend is stronger than NMOS,I_(dsat)decreases by 8.32% and VTHincreases by 6.78%.The physical mechanism of LOD effect is explained.With the decrease of left,the I_(dsat)of NMOS decreases by 9.03%and VTHincreases by 12.5%.The relationship between the electrical parameters of PMOS and left is weaker than that of NMOS,I_(dsat)decreases by 8.50%,and VTHincreases by 4.61%.The cause that the electrical parameters change under WPE effect is proposed.In the nanometer process PDK,the accurate application of LOD and WPE effects can better simulate device performance,and improve the precision of circuit.
引文
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[5] Hung-Chih Ou,Kai-Han Tseng,Jhao-Yan Liu,et al.Layout-Dependent Effects-Aware Analytical Analog Placement[J].IEEE Transactions on Computer-Aided design of integrated circuits and systems,2016,8(35):1243-1254.
[6] SMIC.TD-LO28-SP-2001.28nm Poly SiON Low Power 1P10M1.05V/1.8VSPICE Model(Version 1.1)[S].Joe Li,Aug 2008:49-54.
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