支持高并发访问的新型NVM存储系统
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摘要
I/O系统软件栈是影响NVM存储系统性能的重要因素。针对NVM存储系统的读写速度不均衡、写寿命有限等问题,设计了同异步融合的访问请求管理策略;在使用异步策略管理数据量较大的写操作的同时,仍然使用同步策略管理读请求和少量数据的写请求。针对多核处理器环境下不同计算核心访问存储系统时地址转换开销大的问题,设计了面向多核处理器地址转换缓存策略,减少地址转换的时间开销。最后实现了支持高并发访问NVM存储系统(CNVMS)的原型,并使用通用测试工具进行了随机读写、顺序读写、混合读写和实际应用负载的测试。实验结果表明,与PMBD相比,所提策略能提高1%～22%的读写速度和9%～15%的IOPS,验证了CNVMS策略能有效提高NVM存储系统的I/O性能和访问请求处理速度。
I/O system software stack is an important factor that affects the efficiency of NVM( Non-Volatile Memory)storage system. For NVM storage systems with unbalanced read/write speeds and limited writing lifetimes, new synchronous and asynchronous converged access management strategy was designed. While an asynchronous write cache was implemented by DRAM for the write access to large data, synchronous management strategy was still used for the read access and the write access to small data. Addressing large time overhead of address translation for NVM storage systems by conflict among cores in a computer with multi-core processor, a new address translation cache was designed for multi-core processor to reduce time overhead of address translation. Finally, a prototype of Concurrent NVM Storage system( CNVMS) was implemented, and the universal testing tools were used to test performance of random reads writes, sequential reads writes, mixed reads/writes and with actual application workload. The experimental results show that the proposed strategy increases read and write speed by1%-22% and IOPS( Input/Output operations Per Second) by 9%-15% compared with PMBD( Persistent Memory Block Driver), which verifies that CNVMS strategy can provide higher I/O performance and better access request processing speed.
I/O system software stack is an important factor that affects the efficiency of NVM( Non-Volatile Memory)storage system. For NVM storage systems with unbalanced read/write speeds and limited writing lifetimes, new synchronous and asynchronous converged access management strategy was designed. While an asynchronous write cache was implemented by DRAM for the write access to large data, synchronous management strategy was still used for the read access and the write access to small data. Addressing large time overhead of address translation for NVM storage systems by conflict among cores in a computer with multi-core processor, a new address translation cache was designed for multi-core processor to reduce time overhead of address translation. Finally, a prototype of Concurrent NVM Storage system( CNVMS) was implemented, and the universal testing tools were used to test performance of random reads writes, sequential reads writes, mixed reads/writes and with actual application workload. The experimental results show that the proposed strategy increases read and write speed by1%-22% and IOPS( Input/Output operations Per Second) by 9%-15% compared with PMBD( Persistent Memory Block Driver), which verifies that CNVMS strategy can provide higher I/O performance and better access request processing speed.
引文
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[2]Micron. Mobile LPDDR2-PCM.[EB/OL].[2018-01-08]. http://www. micron. com/products/multichip-packages/pcm-basedmcp.
[3]CAULFIELD A M, COBURN J, MOLLOV T, et al. Understanding the impact of emerging non-volatile memories on high-performance,IO-intensive computing[C]//SC'10:Proceedings of the 2010ACM/IEEE High Performance Computing, Networking, Storage and Analysis. Piscataway, NJ:IEEE, 2010:1-11.
[4]JO S H, KUMAR T, NARAYANAN S, et al. 3D-stackable crossbar resistive memory based on Field Assisted Superlinear Threshold(FAST)selector[C]//Proceedings of the 2014 International Electron Devices Meeting. Piscataway, NJ:IEEE, 2014:6. 7. 1-6. 7.4.
[5]YANG J, MINTURN D B, HADY F. When poll is better than interrupt[C]//Proceedings of the 2010 USENIX Conference on File and Storage Technologies. Berkeley:USENIX Association, 2012:3-3.
[6]DEJAN V, WANG Q B, CYRIL G, et al. DC express:shortest latency protocol for reading phase change memory over PCI express[C]//Proceedings of the 2014 USENIX Conference on File and Storage Technologies. Berkeley:USENIX Association, 2014:17-20.
[7]DULLOOR S R, KUMAR S, KESHAVAMURTHY A, et al. System software for persistent memory[C]//EuroSys 2015:Proceedings of the 10th European Conference on Computer Systems. New York:ACM, 2014:Article No. 15.
[8]OU J X, SHU J W, LU Y Y. A high performance file system for non-volatile main memory[C]//EuroSys 2016:Proceedings of the11th European Conference on Computer Systems. New York:ACM,2016:18-21.
[9]LU Y Y, SHU J W, SUN L. Blurred persistence in transactional persistent memory[C]//Proceedings of the 2015 Mass Storage Systems and Technologies. Piscataway, NJ:IEEE, 2015:1-13.
[10]JIN P Q, WU Z L, WANG X L, et al. A page-based storage framework for phase change memory[C]//Proceedings of the 2017International Conference on Massive Storage Systems and Technology. Piscataway, NJ:IEEE, 2017:152-164.
[11]CAMPELLO D, LOPEZ H, USECHE L, et al. Non-blocking writes to files[C]//Proceedings of the 2015 USENIX Conference on File and Storage Technologies. Berkeley:USENIX Association,2015:151-165.
[12]CAULFIELD A, MOLLOV T, EISNER L, et al. Providing safe,user space access to fast, solid state disks[J]. ACM SIGARCH Computer Architecture News, 2012, 40(1):387-400.
[13]EISNER L A, MOLLOV T, SWANSON S J. Quill:exploiting fast non-volatile memory by transparently bypassing the file system:#CS2013-0991[R]. San Diego:University of California, 2013:127-134.
[14]NIMA E, MOHAMMAD A, ANAND S, et al. Exploiting intra-request slack to improve SSD performance[C]//Proceedings of the2017 International Conference on Architectural Support for Programming Languages and Operating Systems. New York:ACM,2017:375-388.
[15]HARIS V, SANKARALINGAM P, SANKETH N, et al. Storageclass memory needs flexible interfaces[C]//Proceedings of the 4th Asia-Pacific Workshop on Systems. New York:ACM, 2013:Article No. 11.
[16]HARIS V, SANKETH N, SANKARLINGAM P, et al. Aerie:flexible file-system interfaces to storage-class memory[C]//Proceedings of the 2014 European Conference on Computer Systems.New York:ACM, 2014:Article No. 14.
[17]QURESHI M K, SRINIVASAN V, RIVERS J A. Scalable high performance main memory system using phase-change memory technology[J]. ACM SIGARCH Computer Architecture News, 2009,37(3):24-33.
[18]XU J, SWANSON S. NOVA:a log-structured file system for hybrid volatile/non-volatile main memories[C]//Proceedings of the2016 USENIX Conference on File and Storage Technologies.Berkeley:USENIX Association, 2016:22-25.
[19]Intel. Intel 64 and IA-32 architectures software developer's manual[EB/OL].[2018-01-11]. https://software. intel. com/en-us/articles/intel-sdm.
[20]COBURN J, CAULFIELD A, GRUPP L, et al. NVTM:a transactional interface for next-generation non-volatile memories[R]. San Diego:University of California, 2009.
[21]WU X, REDDY A L N. SCMFS:a file system for storage class memory[C]//Proceedings of the 2011 International Conference for High Performance Computing, Networking, Storage and Analysis.New York:ACM, 2011:12-18.
[22]LIU H, CHEN Y, LIAO X, et al. Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures[C]//Proceedings of the 2017 International Conference on High Performance Computing, Networking, Storage and Analysis. New York:ACM,2017:Article No. 26.
[23]CHEN F, MESNIER M P, HAHN S. A protected block device for persistent memory[C]//Proceedings of the 2014 Mass Storage Systems and Technologies. Piscataway, NJ:IEEE, 2014:1-12.