核探测器前端电子学线性稳压器设计
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摘要
根据核探测器前端电子学的特点,改进传统的低压差电压稳压器(Low Drop-Out regulator,LDO)结构,得到对外部电容容值和等效串联电阻(Equivalent Series Resistance,ESR)鲁棒的新型LDO,特别适合于核探测器的前端电子学领域。这一新型LDO结构对负载电容的鲁棒性比较强,而且电压净空低于200 mV,可以提升电源的效率。此外,这一结构电源的负载瞬态恢复时间比较小,小于400 ns,适用于模拟电路和模拟数字混合电路。本设计采用美国IBM公司的130 nm制程互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺,为北京谱议(BESIII)的CGEM(Cylindrical Gas Electron Multipliers)探测器的前端电子学设计做电源供电;并为LHC(Large Hadron Collider)的第三代像素探测器的电源供电做技术储备。
[Background] As nuclear detectors become more and more channels with smaller and smaller volume,front-end electronics tends to adopt CMOS(complementary metal oxide semiconductor) ASIC designs. The ASIC has low power consumption, small parasitic capacitance and small size, hence the power supply has a tendency to integrate at the front end. [Purpose] This study aims to design a new kind of low-dropout(LDO) structure that is suitable for the front-end power supply of nuclear detectors and robust to the process and has no capacitance.[Methods] Based on the classical low-dropout(LDO) structure, complementary metal oxide semiconductor(CMOS)process using IBM 130 nm process was employed to realize the new LDO structure. A novel LDO robust to external capacitance value and equivalent series resistance(ESR) was obtained. This comprehensive performance of the design has the advantage of strong robustnes to load capacitance, hence is siutable for the front end of the nuclear detector. [Results] Its recovery time of the transient response is less than 400 ns and the drop out voltage is below200 m V. All these futures are especially suitable for the front end, which is often a hybrid circuit. [Conclusion] This design is used for the cylindrical gas electron multipliers(CGEM) of BESIII update project, it is also the technical reserve for the power supply of third generation pixel detector in large hadron collider(LHC).
[Background] As nuclear detectors become more and more channels with smaller and smaller volume,front-end electronics tends to adopt CMOS(complementary metal oxide semiconductor) ASIC designs. The ASIC has low power consumption, small parasitic capacitance and small size, hence the power supply has a tendency to integrate at the front end. [Purpose] This study aims to design a new kind of low-dropout(LDO) structure that is suitable for the front-end power supply of nuclear detectors and robust to the process and has no capacitance.[Methods] Based on the classical low-dropout(LDO) structure, complementary metal oxide semiconductor(CMOS)process using IBM 130 nm process was employed to realize the new LDO structure. A novel LDO robust to external capacitance value and equivalent series resistance(ESR) was obtained. This comprehensive performance of the design has the advantage of strong robustnes to load capacitance, hence is siutable for the front end of the nuclear detector. [Results] Its recovery time of the transient response is less than 400 ns and the drop out voltage is below200 m V. All these futures are especially suitable for the front end, which is often a hybrid circuit. [Conclusion] This design is used for the cylindrical gas electron multipliers(CGEM) of BESIII update project, it is also the technical reserve for the power supply of third generation pixel detector in large hadron collider(LHC).
引文
1 Rincon-Mora G A.Analog IC design with low-dropou regulators[M].2nd ed.New York,USA:McGraw-Hill2014.
2 Ivanov V.Design methodology and circuit techniques for any load stable LDO with instant load regulation and low noise//Advanced Analog Circuit Design[M].New York USA:Springer,2008.
3 Reay G.Kovacs an unconditionally stable 2-stage CMOSamplifier[J].IEEE Journal of Solid-State Circuits,199530(5):591-594.DOI:10.1109/4.384174.
4 Hu J,Huijsing J H,Makinwa K A A.A Three-stage amplifier with quenched multipath frequency compensation for all capacitive loads[C].New Orleans Louisiana,USA:IEEE International Symposium on Circuits and Systems,2007:225-228.DOI:10.1109/ISCAS.2007.378317.
5 Gray P R,Hurst P J,Lewis S H,et al.Analysis and design of analog integrated circuits[M].5th ed.New York,USA:Wiley,2009.
6 Razavi B.Design of analog CMOS integrated circuits[M].2nd ed.New York,USA:McGraw-Hill,2016.
7 Kim Y I,Lee S S.A capacitorless LDO regulator with fast feedback technique and low-quiescent current error amplifier[J].Circuits and Systems II:Express Briefs,IEEE Transactions on,2013,60(6):326-330.DOI:10.1109/TCSII.2013.2258250.
8 Maity A,Patra A.Tradeoffs aware design procedure for an adaptively biased capacitorless low dropout regulator using nested miller compensation[J].Power Electronics,IEEE Transactions on,2016,31(1):369-380.DOI:10.1109/tpel.2015.2398868.
9 Hong S W,Cho G H.High-gain wide-bandwidth capacitor-less low-dropout regulator(LDO)for mobile applications utilizing frequency response of multiple feedback loops[J].Circuits and Systems I:Regular Papers,IEEE Transactions on,2016,63(1):46-57.DOI:10.1109/tcsi.2015.2512702.
10 Yoni Y H,Pere L M.Capatitor-free,low drop-out linear regulator in a 180 nm CMOS for hearing aids[C].IEEE Copenhagen,Denmark:Nordic Circuits and Systems Conference,2016.DOI:10.1109/NORCHIP.2016.7792888.
2 Ivanov V.Design methodology and circuit techniques for any load stable LDO with instant load regulation and low noise//Advanced Analog Circuit Design[M].New York USA:Springer,2008.
3 Reay G.Kovacs an unconditionally stable 2-stage CMOSamplifier[J].IEEE Journal of Solid-State Circuits,199530(5):591-594.DOI:10.1109/4.384174.
4 Hu J,Huijsing J H,Makinwa K A A.A Three-stage amplifier with quenched multipath frequency compensation for all capacitive loads[C].New Orleans Louisiana,USA:IEEE International Symposium on Circuits and Systems,2007:225-228.DOI:10.1109/ISCAS.2007.378317.
5 Gray P R,Hurst P J,Lewis S H,et al.Analysis and design of analog integrated circuits[M].5th ed.New York,USA:Wiley,2009.
6 Razavi B.Design of analog CMOS integrated circuits[M].2nd ed.New York,USA:McGraw-Hill,2016.
7 Kim Y I,Lee S S.A capacitorless LDO regulator with fast feedback technique and low-quiescent current error amplifier[J].Circuits and Systems II:Express Briefs,IEEE Transactions on,2013,60(6):326-330.DOI:10.1109/TCSII.2013.2258250.
8 Maity A,Patra A.Tradeoffs aware design procedure for an adaptively biased capacitorless low dropout regulator using nested miller compensation[J].Power Electronics,IEEE Transactions on,2016,31(1):369-380.DOI:10.1109/tpel.2015.2398868.
9 Hong S W,Cho G H.High-gain wide-bandwidth capacitor-less low-dropout regulator(LDO)for mobile applications utilizing frequency response of multiple feedback loops[J].Circuits and Systems I:Regular Papers,IEEE Transactions on,2016,63(1):46-57.DOI:10.1109/tcsi.2015.2512702.
10 Yoni Y H,Pere L M.Capatitor-free,low drop-out linear regulator in a 180 nm CMOS for hearing aids[C].IEEE Copenhagen,Denmark:Nordic Circuits and Systems Conference,2016.DOI:10.1109/NORCHIP.2016.7792888.