基于65 nm工艺的双模自适应连续时间线性均衡器设计
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摘要
描述了一种双模自适应连续时间线性均衡器(CTLE)的结构和电路设计。提出了一种结合HF-Boost、DC-Degeneration模式的双模CTLE,在5 Gb/s数据速率下提供最大的14 dB信道损耗补偿能力。该CTLE能够手动调节,也能进行基于二维眼图监视器算法的完全自适应调节。给出了均衡器电路的晶体管级设计和自适应算法引擎的模块级设计,并给出了仿真和测试结果。芯片采用65 nm高性能CMOS工艺制作,低剖面四边形平面封装。
The design of the architecture and circuits for a dual mode continuous-time linear equalizer(CTLE) was described. A dual-mode CTLE combining with HF-Boost mode and DC-Degeneration mode was proposed, which provided a maximal 14 dB channel loss compensation capability at 5 Gb/s data rate. This CTLE was able to be manual tuning as well as fully adaptive based on a 2-Dimensional eye open monitor. A transistor level design of the equalization circuit and a block level design of the adaptation algorithm engine were described, and the simulation and measure results were given. The chip is fabricated in 65 nm high performance CMOS technology and assembled in a low-profile quad flat package.
The design of the architecture and circuits for a dual mode continuous-time linear equalizer(CTLE) was described. A dual-mode CTLE combining with HF-Boost mode and DC-Degeneration mode was proposed, which provided a maximal 14 dB channel loss compensation capability at 5 Gb/s data rate. This CTLE was able to be manual tuning as well as fully adaptive based on a 2-Dimensional eye open monitor. A transistor level design of the equalization circuit and a block level design of the adaptation algorithm engine were described, and the simulation and measure results were given. The chip is fabricated in 65 nm high performance CMOS technology and assembled in a low-profile quad flat package.
引文
[1]Jaeduk Han,Yue Lu,Nicholas,et al.A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm cmos techology[C].Solid-state Circuits Conference,2017:112-113.
[2]刘玮,肖磊,杨莲兴.1.25Gbps串并并串转换接收器的低抖动设计[J].固体电子学研究与进展,2009,29(1):99-105.
[3]Cai Y,Werner S A,Zhang G J,et al.Jitter testing for multi-gigabit backplane SerDes[C].International Test Conference(ITC 02),IEEE Press,Piscataway,N J,2002:700-710.
[4]Srikanth Gondi,Behzad Razavi.Equalization and clock and data recovery techniques for 10-Gb/s CMOS seriallink receivers[J].IEEE Journal of Solid-state Circuits,2007,42(9):1999-2011.
[5]Tony Shuo-Chun Kao,Faisal A Musa,Anthony Chan Carusone.A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization[J].IEEE Trans Circuits and Systems,2010,43(7):2844-2856,
[6]Hiroshi Kimura,Pervez M Azizet,Tai Jing,et al.A28Gb/s 560 mW multi-standard serdes with singlestage analog front-end and 14-tap decision feedback equalizer in 28nm CMOS[J].IEEE Journal of Solidstate Circuits,2014,49(12):3091-3103.
[7]Lee Y S M,Sheikhaei S,Mirabbasi S,et al.A 10Gb/s active-inductor structure with peakingcontrol in90nm CMOS[C].IEEE ASSCC Dig Tech,2008:229-232.
[8]Behnam Analui,Alexander Rylyakov,Sergey Rylov,et al.A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS[J].IEEE Journal of Solid-state Circuits,2005,40(12):2689-2699.
[2]刘玮,肖磊,杨莲兴.1.25Gbps串并并串转换接收器的低抖动设计[J].固体电子学研究与进展,2009,29(1):99-105.
[3]Cai Y,Werner S A,Zhang G J,et al.Jitter testing for multi-gigabit backplane SerDes[C].International Test Conference(ITC 02),IEEE Press,Piscataway,N J,2002:700-710.
[4]Srikanth Gondi,Behzad Razavi.Equalization and clock and data recovery techniques for 10-Gb/s CMOS seriallink receivers[J].IEEE Journal of Solid-state Circuits,2007,42(9):1999-2011.
[5]Tony Shuo-Chun Kao,Faisal A Musa,Anthony Chan Carusone.A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization[J].IEEE Trans Circuits and Systems,2010,43(7):2844-2856,
[6]Hiroshi Kimura,Pervez M Azizet,Tai Jing,et al.A28Gb/s 560 mW multi-standard serdes with singlestage analog front-end and 14-tap decision feedback equalizer in 28nm CMOS[J].IEEE Journal of Solidstate Circuits,2014,49(12):3091-3103.
[7]Lee Y S M,Sheikhaei S,Mirabbasi S,et al.A 10Gb/s active-inductor structure with peakingcontrol in90nm CMOS[C].IEEE ASSCC Dig Tech,2008:229-232.
[8]Behnam Analui,Alexander Rylyakov,Sergey Rylov,et al.A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS[J].IEEE Journal of Solid-state Circuits,2005,40(12):2689-2699.