热应力对深亚微米SRAM漏电流的影响
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摘要
浅槽隔离(STI)技术广泛应用于深亚微米CMOS集成电路制造,是工艺应力主要的来源之一。CMOS工艺采用牺牲氧化层(SAC OX)、栅氧化层以及退火等多道热工艺过程,由此产生的热应力对集成电路漏电流有重要影响。使用TCAD软件对STI结构应力分布进行了仿真分析,通过分组实验对静态随机存储器(SRAM)芯片静态漏电流进行了测试分析。结果表明,牺牲氧化层工艺引起的热应力是导致SRAM漏电流的主要因素,其工艺温度越高,STI应力减小,芯片的漏电流则越小;而取消牺牲氧化层工艺可以获得更小的应力和漏电流。栅氧化层退火工艺可以有效释放应力并修复应力产生的缺陷,退火温度越高漏电流越小,片内一致性也越好。因此,对热工艺过程进行优化,避免热应力积累,是CMOS集成电路工艺开发过程中要考虑的关键问题之一。
Shallow trench isolation(STI) process is widely used in deep sub-micron CMOS IC process technology, and it's one of the main stress sources. In CMOS process, there are many thermal processes, such as sacrificial oxide(SAC OX), gate dielectric formation and annealing, etc. Thermal stresses that induced by these processes have obvious impact on the leakage current of ICs. Stress distribution of the STI structure was simulated using TCAD software. The static leakage current of the static random access memory(SRAM) was tested and analyzed by experimental splits. The results show that the thermal stresses caused by SAC OX process is the main cause of high leakage current of the SRAM. The stress decreased as the oxidation temperature increasing, which results in the reduction of the leakage current. Less stresses and leakage current can be obtained by eliminating SAC OX process. Gate oxide annealing process can release the accumulated stresses and repair the defects induced by stresses effectively. The higher the annealing temperature, the smaller the leakage current and the better the on-chip consistency. So optimizing thermal process conditions to avoid the accumulation of stress is one of the key factors to be considered during the CMOS IC process development.
Shallow trench isolation(STI) process is widely used in deep sub-micron CMOS IC process technology, and it's one of the main stress sources. In CMOS process, there are many thermal processes, such as sacrificial oxide(SAC OX), gate dielectric formation and annealing, etc. Thermal stresses that induced by these processes have obvious impact on the leakage current of ICs. Stress distribution of the STI structure was simulated using TCAD software. The static leakage current of the static random access memory(SRAM) was tested and analyzed by experimental splits. The results show that the thermal stresses caused by SAC OX process is the main cause of high leakage current of the SRAM. The stress decreased as the oxidation temperature increasing, which results in the reduction of the leakage current. Less stresses and leakage current can be obtained by eliminating SAC OX process. Gate oxide annealing process can release the accumulated stresses and repair the defects induced by stresses effectively. The higher the annealing temperature, the smaller the leakage current and the better the on-chip consistency. So optimizing thermal process conditions to avoid the accumulation of stress is one of the key factors to be considered during the CMOS IC process development.
引文
[1] 李睿,王庆东. 工艺导致的机械应力对深亚微米CMOS器件的影响[J]. 物理学报,2008,57(7):4497-4507.LI R, WANG Q D. Process-induced mechanical stress effects on deep submicron CMOS device [J]. Acta Physica Sinica, 2008, 57(7): 4497-4507(in Chinese).
[2] MENON S, AGAM M. Standby leakage current reduction in a 180 nm EEPROM process technology [C] //Proceedings of Advanced Semiconductor Manufacture Conference. New York, NY,USA, 2015:58-63.
[3] KIM T K, KIM D H, PARK J K, et al. Modeling of cumulative thermo-mechanical stress (CTMS) produced by the shallow trench isolation process for 1 Gb DRAM and beyond [C] // Proceedings of International Electron Devices Meeting. San Francisco, CA, USA, 1998:145-148.
[4] HA D W, CHO C H, SHIN D W, et al. Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices [J]. IEEE Transactions on Electron Devices, 1999, 46(5):940-946.
[5] KUROI T, UCHIDA T, SAKAI M, et al. Stress analysis of shallow trench isolation for 256 M DRAM and beyond[C]// Proceedings of International Electron Devices Meeting. San Francisco, CA, USA, 1998:141-144.
[6] DAMIANO J, SUBRAMANIAN C K, GIBSON M, et al. Characterization an elimination of trench dislocations[C]// Proceedings of Symposium on VLSI Technology.Honolulu, HI, USA, 1998 : 212-213.
[7] SZE S M, NG K K. Physics of semiconductor devices [M].3rd ed. USA: John Wiley & Sons, Inc. 2007:90-98.
[8] TAKAHIRO T, TADASHI Y, MARIKO M, et al. Influence of STI stress on leakage current in buried pn junction [C]//Proceedings of the 13th International Workshop on Junction Technology. Kyoto, Japan, 2013:107-108.
[9] SHIOZAWA K, HORITA K, KUROI T, et al. Impact of STI stress on the junction characteristics [C]// Proceedings of International Workshop on Junction Technology.Tokyo, Japan, 2001:19-20.
[2] MENON S, AGAM M. Standby leakage current reduction in a 180 nm EEPROM process technology [C] //Proceedings of Advanced Semiconductor Manufacture Conference. New York, NY,USA, 2015:58-63.
[3] KIM T K, KIM D H, PARK J K, et al. Modeling of cumulative thermo-mechanical stress (CTMS) produced by the shallow trench isolation process for 1 Gb DRAM and beyond [C] // Proceedings of International Electron Devices Meeting. San Francisco, CA, USA, 1998:145-148.
[4] HA D W, CHO C H, SHIN D W, et al. Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices [J]. IEEE Transactions on Electron Devices, 1999, 46(5):940-946.
[5] KUROI T, UCHIDA T, SAKAI M, et al. Stress analysis of shallow trench isolation for 256 M DRAM and beyond[C]// Proceedings of International Electron Devices Meeting. San Francisco, CA, USA, 1998:141-144.
[6] DAMIANO J, SUBRAMANIAN C K, GIBSON M, et al. Characterization an elimination of trench dislocations[C]// Proceedings of Symposium on VLSI Technology.Honolulu, HI, USA, 1998 : 212-213.
[7] SZE S M, NG K K. Physics of semiconductor devices [M].3rd ed. USA: John Wiley & Sons, Inc. 2007:90-98.
[8] TAKAHIRO T, TADASHI Y, MARIKO M, et al. Influence of STI stress on leakage current in buried pn junction [C]//Proceedings of the 13th International Workshop on Junction Technology. Kyoto, Japan, 2013:107-108.
[9] SHIOZAWA K, HORITA K, KUROI T, et al. Impact of STI stress on the junction characteristics [C]// Proceedings of International Workshop on Junction Technology.Tokyo, Japan, 2001:19-20.