一种评估功率LDMOS散热特性的方法
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摘要
介绍了一种评估功率LDMOS散热特性的方法。在0.18μm BCD工艺平台制作了结构相同、叉指数量不同的LDMOS,并进行了TLP测试。通过对物理机理以及I-V曲线进行分析,发现随着叉指数目的不断增加,归一化的寄生电阻趋近定值。基于此,提出了寄生电阻相对变化因子α的概念,用来表征功率LDMOS的散热特性。最后对测试结果进行计算得到,漂移区长度为0.5μm、叉指宽度为33μm、总栅宽为14.4 mm时,LDMOS的α为0.631。
A method of assessing the thermal-diffusion characteristics of power LDMOS(Lateral Diffusion MOSFET) had been proposed. Several power LDMOSs, which had the same structure but different number of fingers(NoF), had been fabricated in an advanced 0.18 μm BCD(Bipolar/CMOS/DMOS) process, and tested by TLP(Transmission Line Pulse) system. The mechanism of power LDMOSs and the TLP I-V curves had been analyzed. It was found that with the increase of NoF, the normalized resistance was approaching to a constant value. Parasitic resistance relative factor α which indicated the thermal-diffusion characteristics of power LDMOS had been introduced. As a result, a power LDMOS with 0.5 μm N-drift length, 33 μm finger width, and 14.4 mm gate width had a factor α of 0.631.
A method of assessing the thermal-diffusion characteristics of power LDMOS(Lateral Diffusion MOSFET) had been proposed. Several power LDMOSs, which had the same structure but different number of fingers(NoF), had been fabricated in an advanced 0.18 μm BCD(Bipolar/CMOS/DMOS) process, and tested by TLP(Transmission Line Pulse) system. The mechanism of power LDMOSs and the TLP I-V curves had been analyzed. It was found that with the increase of NoF, the normalized resistance was approaching to a constant value. Parasitic resistance relative factor α which indicated the thermal-diffusion characteristics of power LDMOS had been introduced. As a result, a power LDMOS with 0.5 μm N-drift length, 33 μm finger width, and 14.4 mm gate width had a factor α of 0.631.
引文
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[2] MA K,HE N,LISERRE M,et al.Frequency-Domain thermal modeling and characterization of power semiconductor devices [J].IEEE Trans Power Elec,2016,31(10):7183-7193.
[3] KHEMKA V,PARTHASARTATHY V,ZHU R H,et al.A novel technique to decouple electrical and thermal effects in SOA limitation of power LDMOSFET [J].IEEE Elec Dev Lett,2004,25(10):705-707.
[4] CHUNG Y,XU H Z,IDA R,et al.Snapback breakdown dynamics and ESD susceptibility of LDMOS [C] // IEEE Int Reliab Phys Symp.San Jose,CA,USA.2006:352-355.
[5] LI H,CONG M F,LI K,et al.Source engineering on ruggedness and RF performance of n-channel RFLDMOS [J].Microelec Reliab,2018,87:57-63.
[6] MALONY T J,LHURANA N.Transmission line pulsing techniques for circuit modeling of ESD phenomena [C] // Proceed EOS/ESD Symp.Minneapolis,MN,USA.1985,EOS-7:49-54.
[7] ANSI/ESDA/JEDEC JS-001-2017.JEDEC standard for electrostatic discharge sensitivity testing human body model (HBM)-component level [S].2017.
[8] JEON B C,LEE S C,OH J K,et al.ESD characterization of grounded-gate NMOS with 0.35 μm/18 V technology employing transmission line pulser (TLP) test [C] // EOS/ESD Symp.Charlotte,NC,USA.2002:362-372.
[9] THEEUWEN S J C H,QURESHI J H.LDMOS technology for RF power amplifiers [J].IEEE Trans Microwave Theo Tech,2012,60(6):1755-1763.