一种带自校准的12-bit SAR-ADC设计
详细信息    查看全文 | 推荐本文 |
  • 英文篇名:A Design of Self-Calibration 12-bit SAR-ADC
  • 作者:许卫明 ; 张金萍 ; 刘俐 ; 庄志伟
  • 英文作者:XU Weiming;ZHANG Jinping;LIU Li;ZHUANG Zhiwei;China Key System Integrated Circuit Co., Ltd.;
  • 关键词:模数转换器 ; RC混合结构 ; 自校准 ; 逐次逼近
  • 英文关键词:ADC;;RC mixed structure;;self-calibration;;SAR
  • 中文刊名:DYFZ
  • 英文刊名:Electronics & Packaging
  • 机构:中科芯集成电路有限公司;
  • 出版日期:2019-07-23 12:55
  • 出版单位:电子与封装
  • 年:2019
  • 期:v.19;No.195
  • 语种:中文;
  • 页:DYFZ201907006
  • 页数:4
  • CN:07
  • ISSN:32-1709/TN
  • 分类号:22-25
摘要
逐次逼近型模数转换器(SAR-ADC)相比较于其他类型的ADC,具有结构简单、功耗低、所占面积小等优点,在移动终端、可穿戴设备以及物联网传感器中被广泛使用。但随着科技的进步,应用场景往往会对SAR-ADC的精度提出更高的要求。基于UMC 110 nm CMOS工艺设计了一款采用RC混合结构且带自校准功能的12-bit SAR-ADC,提高了转换精度、减小了电路面积。其自校准结构相比较于传统的SAR-ADC能够在消除比较器失调的同时将误差量化,以此可判断失调是否被校准完毕,从而判断在该工艺下此ADC性能是否满足需求。
        Compared with other kinds of analog-to-digital, SAR-ADC takes the advantages of simpler structure,lower power, and smaller area. It is widely used in mobile terminal, wearable devices, and internet of things sensor. However, with the progress of science and technology, application scenarios often raise higher requirements for the accuracy of SAR-ADC. Based on UMC 110 nm CMOS process, a 12-bit SAR-ADC with RC mixed structure and self-calibration is designed, and it improves the conversion precision and reduces circuit area. Compared with the traditional SAR-ADC, the self-calibration structure can quantize the error while eliminating the comparator offset, so as to judge whether the offset is calibrated, and whether the performance of the ADC meets the requirements under the process.
引文
[1]郭树田.数据转换器发展近况[J].微电子学,1998,28(4):224-232.
    [2]郭树田. A/D和D/A转换器发展动态[J].世界产品与技术,2000(6):53-55.
    [3]范亮. 12位电容式逐次逼近型模数转换器的设计[D].上海:上海交通大学,2009.
    [4] WANG X,HUANG H,LI Q. Design considerations of ultralow-voltage self-calibration SAR ADC[J]. IEEE Transactions on Circuits and SystemsⅡ:Express Briefs,2015,62(4):337-341.
    [5]周文婷,李章全. SAR A/D转换器中电容失配问题的分析[J].微电子学,2007,37(2):199-203.
    [6]乔高帅,戴庆元,孙磊,等.基于16位SAR模数转换器的误差校准方法[J]. Micronanoeletronic Technology,2009,46(10),636-639.
    [7] HASSAN H A, HALIN I A, ARIS I B, et al. Design of 8-bit SAR ADC CMOS[R]. IEEE SCOReD, 2009, Malaysia, 272-275.
    [8] BABAYANMASHHADI S,LOTFI R. Analysis and design of a low-voltage low-power double-tail comparator[J]. IEEE Transactions on Very Large Scale Integration Systems,2014, 22(2):343-352.

© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号

地址:北京市海淀区学院路29号 邮编:100083

电话:办公室:(+86 10)66554848;文献借阅、咨询服务、科技查新:66554700