一种高线性无源双平衡混频器
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摘要
设计了一种适用于1.0～2.0 GHz的高线性下变频混频器。电路设计采用了无源双平衡结构,片内集成宽带巴伦、限幅本振放大器、混频核和偏置电路。为了提高混频器的线性度,在对无源双平衡的结构进行分析的基础上,折中选择混频核的晶体管尺寸,并优化了本振放大器输出信号的幅值及上升时间。基于0.35μm BiCMOS工艺进行了设计仿真,芯片面积为0.9 mm×1.8 mm。流片测试结果表明:射频频率1.0～2.0 GHz,对应本振频率1.0～2.0 GHz,最佳本振输入功率为0 dBm,转换增益大于-7.0 dB,射频输入三阶交调大于25 dBm,混频器工作电压为3.3 V,功耗为112 mW。该高线性无源双平衡混频器可满足工程应用。
A high linearity down-conversion mixer operating from 1.0 to 2.0 GHz was designed. The passive double balanced mixer consists of a wideband balun, a limiting local oscillator(LO) amplifier, a mixer core and bias circuits. To improve the linearity of the mixer, based on the analysis of the passive double balanced mixer, the size of the transistor in the mixer core was compromised, the amplitude and rising time of the output signal of the LO amplifier was optimized. The circuit was designed and simulated based on the 0.35 μm BiCMOS process and the chip size is 0.9 mm×1.8 mm. The test results show that when the RF frequency is 1.0-2.0 GHz, corresponding to the LO frequency of 1.0-2.0 GHz, the optimal LO input power is 0 dBm and the conversion gain is above-7.0 dB, the RF input third order intercept point is above 25 dBm. The power consumption of the mixer is 112 mW under a supply voltage of 3.3 V. The designed passive double balanced mixer with high linearity can meet the need of enginee-ring applications.
A high linearity down-conversion mixer operating from 1.0 to 2.0 GHz was designed. The passive double balanced mixer consists of a wideband balun, a limiting local oscillator(LO) amplifier, a mixer core and bias circuits. To improve the linearity of the mixer, based on the analysis of the passive double balanced mixer, the size of the transistor in the mixer core was compromised, the amplitude and rising time of the output signal of the LO amplifier was optimized. The circuit was designed and simulated based on the 0.35 μm BiCMOS process and the chip size is 0.9 mm×1.8 mm. The test results show that when the RF frequency is 1.0-2.0 GHz, corresponding to the LO frequency of 1.0-2.0 GHz, the optimal LO input power is 0 dBm and the conversion gain is above-7.0 dB, the RF input third order intercept point is above 25 dBm. The power consumption of the mixer is 112 mW under a supply voltage of 3.3 V. The designed passive double balanced mixer with high linearity can meet the need of enginee-ring applications.
引文
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[2] 曹小阳.低功耗高线性度下混频器的研究与设计[D].长沙:湖南大学,2013:22-28.
[3] 张贵元.CMOS混频器的研究[D].南京:南京理工大学,2013:12-17.
[4] KOMONI K,SONKUSALE S,DAWE G.Fundamental performance limits and scaling of a CMOS passive double-balanced mixer [C]// Proceedings of Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference.Montreal,QC,Canada,2008:297-300.
[5] KRISHNAMURTHI K.The new party line:power-frequency tradeoff in linear BiCMOS passive mixers for cellular base stations [J].IEEE Microwave Magazine,2014,15(2):79-83.
[6] KRISHNAMURTHI K,LIU Z Y,GRESHAM I.Design of linear SiGe IC downconverters [J].Microwave Journal,2013,56(3):78.
[7] 王腾星.片上集成螺旋变压器和巴伦的优化设计[D].上海:复旦大学,2012:13-18.
[8] HAN S G,CHI B Y,WANG Z H.A high phase accuracy,low amplitude mismatch quadrature LO driver[C] //Proceedings of the 7th International Conference on Solid-State and Integrated Circuits Technology.Beijing,China,2004:1260-1263.