DDR2高速PCB设计和信号完整性分析
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摘要
随着现代高速电路设计的发展,DDR2因其内存强大的预读取能力成为许多嵌入式系统的选择。然而,DDR2的仿真工作不仅繁琐耗时量大,对EMI的仿真也比较困难,给PCB设计也带来了大量的工作难点。文中针对DDR2高速电路中存在的信号完整性问题进行了分析,提出了PCB设计要点。并以单个DDR2存储器与控制器间的PCB设计为例,对如何在减少仿真工作的情况下成功完成一个可用的设计进行了论述。
With the development of modern high speed circuit design, DDR2 has become more designers' choice due to the great pre-reading capability of its memory. However,DDR2 simulation is time consuming,and its simulation of EMI is difficult,which constitute difficulties for PCB design. The problem of signal integrity in high speed circuit DDR2 is analyzed in detail and the key points of design of PCB are put forward. Taking a PCB design of a single DDR2 memory with a controller for instance,this paper describes how to complete an available design successfully with decreased simulation work.
With the development of modern high speed circuit design, DDR2 has become more designers' choice due to the great pre-reading capability of its memory. However,DDR2 simulation is time consuming,and its simulation of EMI is difficult,which constitute difficulties for PCB design. The problem of signal integrity in high speed circuit DDR2 is analyzed in detail and the key points of design of PCB are put forward. Taking a PCB design of a single DDR2 memory with a controller for instance,this paper describes how to complete an available design successfully with decreased simulation work.
引文
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[2]聂琼,钱敏,丁杰.PCB的电磁兼容设计[J].印制电路信息,2010(12):9-12.
[3]高进,韩军杰.基于EDA软件的PCB电磁兼容分析[J].电子产品可靠性与环境试验,2008,26(1):8-12.
[4]俞海珍,冯浩.电磁兼容技术及其在PCB设计中的应用[J].计算机工程与科学,2004,26(4):80-81,105.
[5]吴卫兵,蒋万良.产品的PCB阶段的电磁兼容EMC设计[J].电子质量,2005(8):70-72.
[6]朱葛俊,崔景,张海全.电子设备PCB电磁兼容设计的分析[J].内蒙古电力技术,2005,23(5):26-28.
[7]阮琼,廖红华.高速电路板的信号完整性设计与仿真[J].湖北民族学院学报,2010,28(4):446-449.
[8]朱文龙,钟龙平,廖乐平,等.多层高速PCB中参考平面转换的信号完整性问题研究[J].厦门大学学报,2010,49(5):629-630.
[9]周博远,于立新,褚军舰.IBIS建模和PCB信号完整性分析[J].微电子学与计算机,2010,27(10):111-113.
[10]覃婕,阎波,林水生.基于Cadence_Allegro的高速PCB设计信号完整性分析与仿真[J].现代电子技术,2011,34(10):169-171,178.