实现相位和频率检测解耦的快速锁相环
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摘要
同步旋转坐标锁相环(SRF-PLL)及其改进型锁相环的相位与频率紧密耦合,电压相位发生突变而频率不变的情况下,检测得到的频率会经历一个暂态过程,导致频率检测的不准确。为此,在准一阶锁相环(QT1-PLL)结构基础上,增设解耦单元,提出改进型准一阶锁相环(MT1-PLL),实现相位与频率检测的解耦。为提高MT1-PLL对不对称、谐波等的抗干扰能力,将级联延迟信号消除法(CDSC)滤波与数学运算滤波结合成前置滤波模块,提取基波正序电压。该前置滤波模块能够滤除2次谐波,且整个滤波过程耗时仅为0.635个周期。同时,考虑了电网频率偏移、信号采样频率的影响,采用误差前馈的方法补偿它们在滤波模块造成的相位误差。最后,在PSCAD/EMTDC中设置各种工况,仿真验证了MT1-PLL、滤波模块以及相位误差消除方法的有效性。
Detection of phase and frequency by synchronous reference frame phase-locked loop(SRF-PLL) and its improved versions are closely coupled. If the voltage with an unvaried frequency has a step change in phase angle, the detected frequency will suffer a transient process, causing errors to the detection of frequency. Thus, based on the structure of quasi-type-1 phase-locked loop(QT1-PLL), a modified quasi-type-1 phase-locked loop(MT1-PLL) is proposed with a decoupled unit, which is able to achieve decoupled detection of phase and frequency. In order to improve the ability of MT1-PLL to reject unbalance, harmonics, etc., cascaded delayed signal cancellation(CDSC) is combined with a proposed mathematical filter, forming a pre-loop filtering module to extract fundamental positive sequence voltage. The module features the elimination of 2 nd harmonics, and a fast filter process takes only 0.635 cycles. Meanwhile, the phase errors in the module caused by deviations of grid frequency, and sampling frequency are also considered, which are compensated by an error feedforward method. Finally, simulations are conducted in PSCAD/EMTDC under various operation conditions to verify the effectiveness of MT1-PLL, filtering module and cancellation method of phase error.
Detection of phase and frequency by synchronous reference frame phase-locked loop(SRF-PLL) and its improved versions are closely coupled. If the voltage with an unvaried frequency has a step change in phase angle, the detected frequency will suffer a transient process, causing errors to the detection of frequency. Thus, based on the structure of quasi-type-1 phase-locked loop(QT1-PLL), a modified quasi-type-1 phase-locked loop(MT1-PLL) is proposed with a decoupled unit, which is able to achieve decoupled detection of phase and frequency. In order to improve the ability of MT1-PLL to reject unbalance, harmonics, etc., cascaded delayed signal cancellation(CDSC) is combined with a proposed mathematical filter, forming a pre-loop filtering module to extract fundamental positive sequence voltage. The module features the elimination of 2 nd harmonics, and a fast filter process takes only 0.635 cycles. Meanwhile, the phase errors in the module caused by deviations of grid frequency, and sampling frequency are also considered, which are compensated by an error feedforward method. Finally, simulations are conducted in PSCAD/EMTDC under various operation conditions to verify the effectiveness of MT1-PLL, filtering module and cancellation method of phase error.
引文
[1] FREIJEDO F D, DOVAL-GANDOY J, LOPEZ O, et al. Tuning of phase-locked loops for power converters under distorted utility conditions[J]. IEEE Transactions on Industry Applications, 2009, 45(6): 2039-2047.
[2] GOLESTAN S, GUERRERO J M, VASQUEZ J C. Three-phase PLLs: a review of recent advances[J]. IEEE Transactions on Power Electronics, 2017, 32(3): 1894-1907.
[3] KANJIYA P, KHADKIKAR V, EL MOURSI M S. A novel type-1 frequency-locked loop for fast detection of frequency and phase with improved stability margins[J]. IEEE Transactions on Power Electronics, 2016, 31(3): 2550-2561.
[4] BATISTA Y N, SOUZA H E P D, NEVES F A S, et al. Variable-structure generalized delayed signal cancellation PLL to improve convergence time[J]. IEEE Transactions on Industrial Electronics, 2015, 62(11): 7146-7150.
[5] 姜齐荣,王亮,张春朋,等.基于频率和初相角解耦检测的新型锁相环[J].电力系统自动化,2013,37(18):113-119.JIANG Qirong, WANG Liang, ZHANG Chunpeng, et al. A new phase-locked loop based on decoupled detection of frequency and initial phase angle[J]. Automation of Electric Power Systems, 2013, 37(18): 113-119.
[6] SE-KYO C. A phase tracking system for three phase utility interface inverters[J]. IEEE Transactions on Power Electronics, 2000, 15(3): 431-438.
[7] GARDNER F M. Phaselock techniques[M]. USA: John Wiley & Sons, 2005.
[8] RODRíGUEZ P, POU J, BERGAS J, et al. Decoupled double synchronous reference frame PLL for power ponverters control[J]. IEEE Transactions on Power Electronics, 2007, 22(2): 9.
[9] 李珊瑚,杜雄,王莉萍,等.解耦多同步参考坐标系电网电压同步信号检测方法[J].电工技术学报,2011,26(12):183-189.LI Shanhu, DU Xiong, WANG Liping, et al. A grid voltage synchronization method based on decoupled multiple synchronous reference frame[J]. Transactions of China Electrotechnical Society, 2011, 26(12): 183-189.
[10] RODRíGUEZ P, TEODORESCU R, CANDELA I, et al. New positive-sequence voltage detector for grid synchronization of power converters under faulty grid conditions[C]// 2006 37th IEEE Power Electronics Specialists Conference, June 18-22, 2006, Jeju, South Korea: 1-7.
[11] 胡应占,郭素娜.适用于电网不平衡时的广义积分器锁相环设计[J].电力系统保护与控制,2014,42(11):148-154.HU Yingzhan, GUO Suna. Design of generalized integrator phase locked loop for unbalanced grid[J]. Power System Protection and Control, 2014, 42(11): 148-154.
[12] RODRIGUEZ P, LUNA A, ETXEBERRíA I, et al. Multiple second order generalized integrators for harmonic synchronization of power converters[C]// Energy Conversion Congress and Exposition, 2009, San Jose, USA: 2239-2246.
[13] GUO X, WU W, CHEN Z. Multiple-complex coefficient-filter-based phase-locked loop and synchronization technique for three-phase grid-interfaced converters in distributed utility networks[J]. IEEE Transactions on Industrial Electronics, 2011, 58(4): 1194-1204.
[14] 涂娟,汤宁平.基于改进型DSOGI-PLL的电网电压同步信号检测[J].中国电机工程学报,2016,36(9):2350-2356.TU Juan, TANG Ningping. Synchronization signal detection for grid voltage based on modified DSOGI-PLL[J]. Proceedings of the CSEE, 2016, 36(9): 2350-2356.
[15] 李林,郭源博,张晓华.复杂电网工况下基于CDSOGI-SPLL的电网电压同步方法[J].电力系统自动化,2017,41(16):151-157.DOI: 10.7500/AEPS20161130016.LI Lin, GUO Yuanbo, ZHANG Xiaohua. Grid voltage synchronization method based on CDSOGI-SPLL under complex power grid conditions[J]. Automation of Electric Power Systems, 2017, 41(16): 151-157. DOI: 10.7500/AEPS20161130016.
[16] 杜雄,郭宏达,孙鹏菊,等.基于ANF-PLL的电网电压基波正负序分离方法[J].中国电机工程学报,2013,33(27):28-35.DU Xiong, GUO Hongda, SUN Pengju, et al. A positive and negative sequence component separation method for grid voltage based on phase locked loop with an adaptive notch filter[J]. Proceedings of the CSEE, 2013, 33(27): 28-35.
[17] SVENSSON J, BONGIORNO M, SANNINO A. Practical implementation of delayed signal cancellation method for phase-sequence separation[J]. IEEE Transactions on Power Delivery, 2007, 22(1): 18-26.
[18] WANG Y F, LI Y W. Grid synchronization PLL based on cascaded delayed signal cancellation[J]. IEEE Transactions on Power Electronics, 2011, 26(7): 1987-1997.
[19] WANG Y F, LI Y W. Analysis and digital implementation of cascaded delayed signal cancellation PLL[J]. IEEE Transactions on Power Electronics, 2011, 26(4): 1067-1080.
[20] WANG Y F, LI Y W. Three-phase cascaded delayed signal cancellation PLL for fast selective harmonic detection[J]. IEEE Transactions on Industrial Electronics, 2013, 60(4): 1452-1463.
[21] GOLESTAN S, RAMEZANI M, GUERRERO J M, et al. DQ-frame cascaded delayed signal cancellation-based PLL: analysis, design, and comparison with moving average filter-based PLL[J]. IEEE Transactions on Power Electronics, 2015, 30(3): 1618-1632.
[22] HAMED H A, ABDOU A F, BAYOUMI E H E, et al. Frequency adaptive CDSC-PLL using axis drift control under adverse grid condition[J]. IEEE Transactions on Industrial Electronics, 2017, 64(4): 2671-2682.
[23] GOLESTAN S, GUERRERO J M, ABUSORRAH A M, et al. Hybrid synchronous/stationary reference-frame-filtering-based PLL[J]. IEEE Transactions on Industrial Electronics, 2015, 62(8): 5018-5022.
[24] SUBRAMANIAN C, KANAGARAJ R. Rapid tracking of grid variables using prefiltered synchronous reference frame PLL[J]. IEEE Transactions on Instrumentation and Measurement, 2015, 64(7): 1826-1836.
[25] GOLESTAN S, FREIJEDO F D, VIDAL A, et al. A quasi-type-1 phase-locked loop structure[J]. IEEE Transactions on Power Electronics, 2014, 29(12): 6264-6270.
[26] GOLESTAN S, GUERRERO J M, VASQUEZ J C. Hybrid adaptive/nonadaptive delayed signal cancellation-based phase-locked loop[J]. IEEE Transactions on Industrial Electronics, 2017, 64(1): 470-479.
[27] 孙绍华.不平衡电网条件下并网逆变关键技术研究[D].哈尔滨:哈尔滨工业大学,2015.SUN Shaohua. Key techniques of grid-connected inversion under unbalanced grid conditions[D]. Harbin: Harbin Institute of Technology, 2015.
[28] GOLESTAN S, EBRAHIMZADEH E, GUERRERO J M, et al. An adaptive least-error squares filter-based phase-locked loop for synchronization and signal decomposition purposes[J]. IEEE Transactions on Industrial Electronics, 2017, 64(1): 336-346.
[29] 中国电力科学研究院,机械标准化研究所,国家电力调度中心,等.电能质量电力系统频率允许偏差:GB/T 15945—1995[S].北京:中国标准出版社,1995.China Electric Power Research Institute, Machinery Standard Research Institute, Control Center of State Grid, et al. Power quality: permissible deviation of frequency for power system: GB/T 15945—1995[S]. Beijing: Standards Press of China, 1995.
[30] GOLESTAN S, FREIJEDO F D, VIDAL A, et al. An efficient implementation of generalized delayed signal cancellation PLL[J]. IEEE Transactions on Power Electronics, 2016, 31(2): 1085-1094.
[2] GOLESTAN S, GUERRERO J M, VASQUEZ J C. Three-phase PLLs: a review of recent advances[J]. IEEE Transactions on Power Electronics, 2017, 32(3): 1894-1907.
[3] KANJIYA P, KHADKIKAR V, EL MOURSI M S. A novel type-1 frequency-locked loop for fast detection of frequency and phase with improved stability margins[J]. IEEE Transactions on Power Electronics, 2016, 31(3): 2550-2561.
[4] BATISTA Y N, SOUZA H E P D, NEVES F A S, et al. Variable-structure generalized delayed signal cancellation PLL to improve convergence time[J]. IEEE Transactions on Industrial Electronics, 2015, 62(11): 7146-7150.
[5] 姜齐荣,王亮,张春朋,等.基于频率和初相角解耦检测的新型锁相环[J].电力系统自动化,2013,37(18):113-119.JIANG Qirong, WANG Liang, ZHANG Chunpeng, et al. A new phase-locked loop based on decoupled detection of frequency and initial phase angle[J]. Automation of Electric Power Systems, 2013, 37(18): 113-119.
[6] SE-KYO C. A phase tracking system for three phase utility interface inverters[J]. IEEE Transactions on Power Electronics, 2000, 15(3): 431-438.
[7] GARDNER F M. Phaselock techniques[M]. USA: John Wiley & Sons, 2005.
[8] RODRíGUEZ P, POU J, BERGAS J, et al. Decoupled double synchronous reference frame PLL for power ponverters control[J]. IEEE Transactions on Power Electronics, 2007, 22(2): 9.
[9] 李珊瑚,杜雄,王莉萍,等.解耦多同步参考坐标系电网电压同步信号检测方法[J].电工技术学报,2011,26(12):183-189.LI Shanhu, DU Xiong, WANG Liping, et al. A grid voltage synchronization method based on decoupled multiple synchronous reference frame[J]. Transactions of China Electrotechnical Society, 2011, 26(12): 183-189.
[10] RODRíGUEZ P, TEODORESCU R, CANDELA I, et al. New positive-sequence voltage detector for grid synchronization of power converters under faulty grid conditions[C]// 2006 37th IEEE Power Electronics Specialists Conference, June 18-22, 2006, Jeju, South Korea: 1-7.
[11] 胡应占,郭素娜.适用于电网不平衡时的广义积分器锁相环设计[J].电力系统保护与控制,2014,42(11):148-154.HU Yingzhan, GUO Suna. Design of generalized integrator phase locked loop for unbalanced grid[J]. Power System Protection and Control, 2014, 42(11): 148-154.
[12] RODRIGUEZ P, LUNA A, ETXEBERRíA I, et al. Multiple second order generalized integrators for harmonic synchronization of power converters[C]// Energy Conversion Congress and Exposition, 2009, San Jose, USA: 2239-2246.
[13] GUO X, WU W, CHEN Z. Multiple-complex coefficient-filter-based phase-locked loop and synchronization technique for three-phase grid-interfaced converters in distributed utility networks[J]. IEEE Transactions on Industrial Electronics, 2011, 58(4): 1194-1204.
[14] 涂娟,汤宁平.基于改进型DSOGI-PLL的电网电压同步信号检测[J].中国电机工程学报,2016,36(9):2350-2356.TU Juan, TANG Ningping. Synchronization signal detection for grid voltage based on modified DSOGI-PLL[J]. Proceedings of the CSEE, 2016, 36(9): 2350-2356.
[15] 李林,郭源博,张晓华.复杂电网工况下基于CDSOGI-SPLL的电网电压同步方法[J].电力系统自动化,2017,41(16):151-157.DOI: 10.7500/AEPS20161130016.LI Lin, GUO Yuanbo, ZHANG Xiaohua. Grid voltage synchronization method based on CDSOGI-SPLL under complex power grid conditions[J]. Automation of Electric Power Systems, 2017, 41(16): 151-157. DOI: 10.7500/AEPS20161130016.
[16] 杜雄,郭宏达,孙鹏菊,等.基于ANF-PLL的电网电压基波正负序分离方法[J].中国电机工程学报,2013,33(27):28-35.DU Xiong, GUO Hongda, SUN Pengju, et al. A positive and negative sequence component separation method for grid voltage based on phase locked loop with an adaptive notch filter[J]. Proceedings of the CSEE, 2013, 33(27): 28-35.
[17] SVENSSON J, BONGIORNO M, SANNINO A. Practical implementation of delayed signal cancellation method for phase-sequence separation[J]. IEEE Transactions on Power Delivery, 2007, 22(1): 18-26.
[18] WANG Y F, LI Y W. Grid synchronization PLL based on cascaded delayed signal cancellation[J]. IEEE Transactions on Power Electronics, 2011, 26(7): 1987-1997.
[19] WANG Y F, LI Y W. Analysis and digital implementation of cascaded delayed signal cancellation PLL[J]. IEEE Transactions on Power Electronics, 2011, 26(4): 1067-1080.
[20] WANG Y F, LI Y W. Three-phase cascaded delayed signal cancellation PLL for fast selective harmonic detection[J]. IEEE Transactions on Industrial Electronics, 2013, 60(4): 1452-1463.
[21] GOLESTAN S, RAMEZANI M, GUERRERO J M, et al. DQ-frame cascaded delayed signal cancellation-based PLL: analysis, design, and comparison with moving average filter-based PLL[J]. IEEE Transactions on Power Electronics, 2015, 30(3): 1618-1632.
[22] HAMED H A, ABDOU A F, BAYOUMI E H E, et al. Frequency adaptive CDSC-PLL using axis drift control under adverse grid condition[J]. IEEE Transactions on Industrial Electronics, 2017, 64(4): 2671-2682.
[23] GOLESTAN S, GUERRERO J M, ABUSORRAH A M, et al. Hybrid synchronous/stationary reference-frame-filtering-based PLL[J]. IEEE Transactions on Industrial Electronics, 2015, 62(8): 5018-5022.
[24] SUBRAMANIAN C, KANAGARAJ R. Rapid tracking of grid variables using prefiltered synchronous reference frame PLL[J]. IEEE Transactions on Instrumentation and Measurement, 2015, 64(7): 1826-1836.
[25] GOLESTAN S, FREIJEDO F D, VIDAL A, et al. A quasi-type-1 phase-locked loop structure[J]. IEEE Transactions on Power Electronics, 2014, 29(12): 6264-6270.
[26] GOLESTAN S, GUERRERO J M, VASQUEZ J C. Hybrid adaptive/nonadaptive delayed signal cancellation-based phase-locked loop[J]. IEEE Transactions on Industrial Electronics, 2017, 64(1): 470-479.
[27] 孙绍华.不平衡电网条件下并网逆变关键技术研究[D].哈尔滨:哈尔滨工业大学,2015.SUN Shaohua. Key techniques of grid-connected inversion under unbalanced grid conditions[D]. Harbin: Harbin Institute of Technology, 2015.
[28] GOLESTAN S, EBRAHIMZADEH E, GUERRERO J M, et al. An adaptive least-error squares filter-based phase-locked loop for synchronization and signal decomposition purposes[J]. IEEE Transactions on Industrial Electronics, 2017, 64(1): 336-346.
[29] 中国电力科学研究院,机械标准化研究所,国家电力调度中心,等.电能质量电力系统频率允许偏差:GB/T 15945—1995[S].北京:中国标准出版社,1995.China Electric Power Research Institute, Machinery Standard Research Institute, Control Center of State Grid, et al. Power quality: permissible deviation of frequency for power system: GB/T 15945—1995[S]. Beijing: Standards Press of China, 1995.
[30] GOLESTAN S, FREIJEDO F D, VIDAL A, et al. An efficient implementation of generalized delayed signal cancellation PLL[J]. IEEE Transactions on Power Electronics, 2016, 31(2): 1085-1094.