一种性能指标可配置的SAR ADC的设计与实现
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摘要
提出了一种分辨率、电源电压等性能指标可配置的逐次逼近寄存器型(SAR)模数转换器(ADC)的设计思想和实现方式。分析了SAR ADC的采样速率、精度、功耗和能量效率等主要性能指标之间的关系,提出了性能参数可配置SAR ADC的设计构想。介绍了性能指标可配置SAR ADC的实现方式,包括分辨率的配置、采样速率的可变以及电源电压的可调等。基于0.18μm CMOS工艺完成了ADC的版图设计、工艺加工和性能参数测试,ADC核心部分芯片面积仅为360μm×550μm。测试结果表明,SAR ADC的分辨率为6～10 bit、电源电压为0.5～0.9 V,在10 bit模式以及0.5 V电源电压下,该SAR ADC信噪失真比(SNDR)和无杂散动态范围(SFDR)分别可达到56.36 dB和67.96 dB,采样速率可达到2 MS/s,能量效率优值(FOM)为20.6 fJ/conversion-step。
Design ideas and implementation ways of a successive approximation register(SAR) analog-to-digital converter(ADC) with configurable performance specifications such as the resolution and power supply voltage were presented. The relationships among the sampling rate, precision, power consumption and energy efficiency of the SAR DAC were analyzed. The design concept of the performance parameters configurable SAR ADC was proposed. The implementation ways of the performance specifications configurable SAR DAC were introduced, including the resolution configuration, variable sampling rate and adjustable power supply voltage. Based on 0.18 μm CMOS process, the layout design, proces-sing and performance parameters testing of the ADC were completed. The core chip area of the ADC is only 360 μm× 550 μm. The test results show that the resolution and power supply voltage of the SAR ADC are 6-10 bit and 0.5-0.9 V,respectively. At 10 bit mode and 0.5 V power supply voltage, the proposed SAR ADC achieves a signal-to-noise-distortion ratio(SNDR) of 56.36 dB and a spurious-free dynamic range(SFDR) of 67.96 dB, respectively, and the sampling rate can reach 2 MS/s, corresponding to an energy efficiency figure-of-merit(FOM) of 20.6 fJ/conversion-step.
Design ideas and implementation ways of a successive approximation register(SAR) analog-to-digital converter(ADC) with configurable performance specifications such as the resolution and power supply voltage were presented. The relationships among the sampling rate, precision, power consumption and energy efficiency of the SAR DAC were analyzed. The design concept of the performance parameters configurable SAR ADC was proposed. The implementation ways of the performance specifications configurable SAR DAC were introduced, including the resolution configuration, variable sampling rate and adjustable power supply voltage. Based on 0.18 μm CMOS process, the layout design, proces-sing and performance parameters testing of the ADC were completed. The core chip area of the ADC is only 360 μm× 550 μm. The test results show that the resolution and power supply voltage of the SAR ADC are 6-10 bit and 0.5-0.9 V,respectively. At 10 bit mode and 0.5 V power supply voltage, the proposed SAR ADC achieves a signal-to-noise-distortion ratio(SNDR) of 56.36 dB and a spurious-free dynamic range(SFDR) of 67.96 dB, respectively, and the sampling rate can reach 2 MS/s, corresponding to an energy efficiency figure-of-merit(FOM) of 20.6 fJ/conversion-step.
引文
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[5] ZHANG D,BHIDE A,ALVANDPOUR A.A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices [J].IEEE Journal of Solid-State Circuits,2012,47(7):1585-1593.
[6] 王浩.低功耗电荷重分配式CMOS逐次逼近型模数转换器研究 [D].西安:西安电子科技大学,2016:94-95.
[7] WAKIMOTO T,LI H X,MURASE K.Statistical analysis on the effect of capacitance mismatch in a high-resolution successive-approximation ADC [J].IEEJ Transactions on Electrical and Electronic Engineering,2011,6(S1):S89-S93.
[8] HARPE P,DOLMANS G,PHIPIPS K,et al.A 0.7 V 7-to-10 bit 0-to-2 MS/s flexible SAR ADC for ultra low-power wireless sensor nodes [C] // Proceedings of the ESSCIRC.Bordeaux,France,2012:373-376.
[9] YIP M,CHANDRAKASAN A P.A resolution-reconfigurable 5-to-10-bit 0.4-to-1 V power scalable SAR ADC for sensor applications [J].IEEE Journal of Solid-State Circuits,2013,48(6):1453-1464.
[10] HARPE P,ZHANG Y,DOLMANS G,et al.A 7-to-10 bit 0-to-4 MS/s flexible SAR ADC with 6.5-to-16 fJ/conversion-step [C] // Proceedings of IEEE International Solid-State Circuits Conference.San Francisco,CA,USA,2012:472-474.
[2] 居水荣,魏天尧,朱樟明.超低功耗逐次逼近寄存器型模数转换器的设计 [J].半导体技术,2015,40(3):174-181.JU S R,WEI T Y,ZHU Z M.Design of ultra low power SAR ADC [J].Semiconductor Technology,2015,40(3):174-181(in Chinese).
[3] GINSBURG B P,CHANDRAKASAN A P.An energy-efficient charge recycling approach for a SAR converter with capacitive DAC [C] // Proceedings of IEEE International Symposium on Circuits and Systems.Kobe,Japan,2005:184-187.
[4] 肖余.纳米级低功耗SAR A/D转换器设计研究 [D].西安:西安电子科技大学,2014:32-33.
[5] ZHANG D,BHIDE A,ALVANDPOUR A.A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices [J].IEEE Journal of Solid-State Circuits,2012,47(7):1585-1593.
[6] 王浩.低功耗电荷重分配式CMOS逐次逼近型模数转换器研究 [D].西安:西安电子科技大学,2016:94-95.
[7] WAKIMOTO T,LI H X,MURASE K.Statistical analysis on the effect of capacitance mismatch in a high-resolution successive-approximation ADC [J].IEEJ Transactions on Electrical and Electronic Engineering,2011,6(S1):S89-S93.
[8] HARPE P,DOLMANS G,PHIPIPS K,et al.A 0.7 V 7-to-10 bit 0-to-2 MS/s flexible SAR ADC for ultra low-power wireless sensor nodes [C] // Proceedings of the ESSCIRC.Bordeaux,France,2012:373-376.
[9] YIP M,CHANDRAKASAN A P.A resolution-reconfigurable 5-to-10-bit 0.4-to-1 V power scalable SAR ADC for sensor applications [J].IEEE Journal of Solid-State Circuits,2013,48(6):1453-1464.
[10] HARPE P,ZHANG Y,DOLMANS G,et al.A 7-to-10 bit 0-to-4 MS/s flexible SAR ADC with 6.5-to-16 fJ/conversion-step [C] // Proceedings of IEEE International Solid-State Circuits Conference.San Francisco,CA,USA,2012:472-474.