一种多路输出带斩波的带隙基准电路
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  • 英文篇名:A multi-output bandgap of reference voltage circuit with chopping
  • 作者:丁玲 ; 李长猛
  • 英文作者:DING Ling;LI Chang-meng;Beijing Huada Empyrean Software Co., Ltd;
  • 关键词:带隙基准电路 ; 斩波技术 ; 多路输出
  • 英文关键词:Bandgap reference circuit;;Chopping technology;;Multi-output
  • 中文刊名:JCDI
  • 英文刊名:China Integrated Circuit
  • 机构:北京华大九天软件有限公司;
  • 出版日期:2019-05-05
  • 出版单位:中国集成电路
  • 年:2019
  • 期:v.28;No.240
  • 语种:中文;
  • 页:JCDI201905006
  • 页数:7
  • CN:05
  • ISSN:11-5209/TN
  • 分类号:28-34
摘要
带隙基准电路可以在电源电压、温度工艺的变化环境中产生稳定的参考电压,广泛应用于模拟集成电路、数模混合集成电路和系统集成芯片(SOC)中,其精度决定了整个系统的精度和良率。带隙基准电路有许多性能指标参数,如温度系数曲线,基准值的精度,电路的功耗、电源抑制比等。另外带隙基准电路的难点是电路中存在多个简并点,电路的启动问题是难点也是重点。
        Bandgap reference circuit can generate stable reference voltage in the changing environment of power supply voltage, temperature and process. It is widely used in analog integrated circuit, digital-analog hybrid integrated circuit and system integration chip(SOC). Its accuracy determines the accuracy and yield of the whole system.Bandgap reference circuit has many performance parameters, such as temperature coefficient curve, accuracy of reference value, circuit power consumption, power rejection ratio and so on. In addition, the difficulty of bandgap reference circuit is that there are many degenerate points in the circuit, and the starting of the circuit is also the key point.
引文
[1]陈铖颖,杨丽琼,王统主编.CMOS模拟集成电路设计与仿真实例—基于Cadence ADE.电子工业出版社,2013.
    [2]毕查德.拉扎维(陈贵灿译)。模拟CMOS集成电路设计.西安:西安交通大学出版社,2003.
    [3]吴金,姚建楠,常昌远编著。CMOS模拟IP线性集成电路.东南大学出版社,2007.
    [4]Hironoro Banba, A CMOS Bandgap Reference Circuit with Sub-1-V Operation. IEEE J. Solid-state Cirsuits,vol.34,NO.5, pp.670-673, MAY 1999.
    [5] Ka Nang Leung and K. T. Mok. A Sub-1-V 15-ppm/℃CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Device.IEEE J. Solid-state Cirsuits, vol.37, NO.4, pp.526-530, APRIL 2002
    [6]曾健平,邹韦华,易峰等。高电源抑制比带隙基准电压源的设计[J].半导体技术,2007,32(11):984-987.

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