新型Costas环在2PSK中的研究与硬件实现
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  • 英文篇名:Analysis and Implementation of Modified Costas Loop for 2PSK
  • 作者:梁源 ; 王兴华 ; 向新
  • 英文作者:LIANG Yuan;WANG Xing-hua;XIANG Xin;Engineering College of Aeronautics and Astronautics,Air Force Engineering University;
  • 关键词:2PSK ; 载波同步 ; 科斯塔斯环 ; 硬件在环协同
  • 英文关键词:2PSK carrier wave synchronization Costas loop hardware-in-the-loop co-simulation
  • 中文刊名:KXJS
  • 英文刊名:Science Technology and Engineering
  • 机构:空军工程大学航空航天工程学院;
  • 出版日期:2014-07-18
  • 出版单位:科学技术与工程
  • 年:2014
  • 期:v.14;No.309
  • 基金:陕西省自然科学基础研究项目(2009JM8001-4);; 航空科学基金(20095596014)资助
  • 语种:中文;
  • 页:KXJS201420047
  • 页数:5
  • CN:20
  • ISSN:11-4688/T
  • 分类号:243-246+268
摘要
针对先验概率相等的2PSK中的信号不含载波分量,无法通过常规锁相法进行载波同步的缺陷,提出了利用新型科斯塔斯(Costas)环对2PSK进行锁频的方案。利用Simulink搭建框图平台对理论进行了验证,并通过System Generator自动代码生成并将代码下载到FPGA芯片上,同时通过硬件在环协同仿真功能将结果实时在Simulink平台显示出来。输出结果表明该方法能较好地达到实现锁频目的,通过比特流数据实时下载到FPGA开发板来进行调试与验证,提高系统性能。
        A new Modified Costas loop was proposed to achieve carrier wave synchronization for 2PSK with equal prior probability,as the conventional PLL can't make it due to the absence of the carrier partition. Blocks are built in Simulink,and System Generator is also used to generate code automatically and download it into FPGA.Hardware-In-the-Loop co-simulation is implemented to output the results in the Simulink simultaneously. Finally,the results prove that the design can lock the carrier frequency well,and the performance can be enhanced through real-time debug and test to download bitstream into FPGA.
引文
1 樊昌信,曹丽娜.通信原理.北京:国防工业出版社,2010:405 —412Fan Changxin,Cao Lina.CommunicationTheory.Beijing:National Defence of Industry Press,2010:405—412
    2 郑继禹,张厥盛,万心平,等.锁相技术.西安:西安电子科技大学出版社,2012:93—100Zheng Jiyu,Zhang Juesheng,Wan Xinping,et al.Phase lock technology.Xi'an:Xi'an Electronic Science&Technology University Press,2012:93—100
    3 Homes J K.Coherent spread spectrum systems.John Wiley&Sons,1982
    4 陈荣,管吉兴,张喜明.数字Costas环的设计与实现.无线电工程,2010;40(3):24—26Chen Rong,Guan Jixing,Zhang Ximing.Design and implementation of digital costas loop.Radio Engineering,2010;40(3):24—26
    5 Mondal K,Mitra S.Non-recursive decimation filters with arbitrary integer decimation factorp.IET Journals&Magazines,2012;6(3):141 —151
    6 田耘,徐文波.Xilinx FPGA开发使用教程.北京:清华大学出版社,2008Tian Yun,Xu Wenbo.Practical development tutorial for Xilinx FPGA.Beijing:Tsinghua University Press,2008

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